drivers/scsi/tmscsim.h

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 1 /***********************************************************************
 2 ;* File Name : TMSCSIM.H *
 3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
 4 ;* Device Driver *
 5 ;***********************************************************************/
 6 /* $Id: tmscsim.h,v 2.4 1998/12/25 17:33:27 garloff Exp $ */
 7
 8 #ifndef _TMSCSIM_H
 9 #define _TMSCSIM_H
 10
 11 #define IRQ_NONE 255
 12
 13 #define MAX_ADAPTER_NUM 4
 14 #define MAX_SG_LIST_BUF 16
 15 #define MAX_CMD_PER_LUN 8
 16 #define MAX_CMD_QUEUE 2*MAX_CMD_PER_LUN+1
 17 #define MAX_SCSI_ID 8
 18 #define MAX_SRB_CNT MAX_CMD_QUEUE+1/* Max number of started commands */
 19 #define END_SCAN 2
 20
 21 #define SEL_TIMEOUT 153/* 250 ms selection timeout (@ 40 MHz) */
 22
 23 typedefunsigned char UCHAR;
 24 typedefunsigned short USHORT;
 25 typedefunsigned long ULONG;
 26 typedefunsigned int UINT;
 27
 28 typedef UCHAR *PUCHAR;
 29 typedef USHORT *PUSHORT;
 30 typedef ULONG *PULONG;
 31 typedef Scsi_Host_Template *PSHT;
 32 typedefstruct Scsi_Host *PSH;
 33 typedef Scsi_Device *PSCSIDEV;
 34 typedef Scsi_Cmnd *PSCSICMD;
 35 typedefvoid*PVOID;
 36 typedefstruct scatterlist *PSGL, SGL;
 37
 38
 39 /*;-----------------------------------------------------------------------*/
 40 typedefstruct _SyncMsg
 41 {
 42 UCHAR ExtendMsg;
 43 UCHAR ExtMsgLen;
 44 UCHAR SyncXferReq;
 45 UCHAR Period;
 46 UCHAR ReqOffset;
 47 } SyncMsg;
 48 /*;-----------------------------------------------------------------------*/
 49 typedefstruct _Capacity
 50 {
 51 ULONG BlockCount;
 52 ULONG BlockLength;
 53 } Capacity;
 54 /*;-----------------------------------------------------------------------*/
 55 typedefstruct _SGentry
 56 {
 57 ULONG SGXferDataPtr;
 58 ULONG SGXferDataLen;
 59 } SGentry;
 60
 61 typedefstruct _SGentry1
 62 {
 63 ULONG SGXLen;
 64 ULONG SGXPtr;
 65 } SGentry1, *PSGE;
 66
 67
 68 /*
 69 ;-----------------------------------------------------------------------
 70 ; SCSI Request Block
 71 ;-----------------------------------------------------------------------
 72 */
 73 struct _SRB
 74 {
 75 UCHAR CmdBlock[12];
 76
 77 struct _SRB *pNextSRB;
 78 struct _DCB *pSRBDCB;
 79 PSCSICMD pcmd;
 80 PSGL pSegmentList;
 81
 82 ULONG Segment0[2];
 83 ULONG Segment1[2];
 84
 85 /* 0x2c:*/
 86 ULONG TotalXferredLen;
 87 ULONG SGBusAddr;/*;a segment starting address as seen by AM53C974A*/
 88 ULONG SGToBeXferLen;/*; to be xfer length */
 89 ULONG SRBState;
 90
 91 /* 0x3c: */
 92 UCHAR MsgInBuf[6];
 93 UCHAR MsgOutBuf[6];
 94
 95 /* 0x48: */
 96 SGL Segmentx;/* make a one entry of S/G list table */
 97
 98 UCHAR ScsiCmdLen;
 99 UCHAR ScsiPhase;
 100
 101 UCHAR AdaptStatus;
 102 UCHAR TargetStatus;
 103
 104 /* 0x58: */
 105 UCHAR MsgCnt;
 106 UCHAR EndMessage;
 107 UCHAR RetryCnt;
 108 UCHAR SRBFlag;/*; b0-AutoReqSense,b6-Read,b7-write */
 109 /*; b4-settimeout,b5-Residual valid */
 110 UCHAR TagNumber;
 111 UCHAR SGcount;
 112 UCHAR SGIndex;
 113 UCHAR SRBStatus;
 114 //UCHAR IORBFlag; /*;81h-Reset, 2-retry */
 115
 116 /* 0x60: */
 117 };
 118
 119
 120 typedefstruct _SRB DC390_SRB, *PSRB;
 121
 122 /*
 123 ;-----------------------------------------------------------------------
 124 ; Device Control Block
 125 ;-----------------------------------------------------------------------
 126 */
 127 struct _DCB
 128 {
 129 struct _DCB *pNextDCB;
 130 struct _ACB *pDCBACB;
 131
 132 PSCSICMD pQIORBhead;
 133 PSCSICMD pQIORBtail;
 134 PSCSICMD AboIORBhead;
 135 PSCSICMD AboIORBtail;
 136 ULONG QIORBCnt;
 137 ULONG AboIORBcnt;
 138
 139 /* 0x20: */
 140 PSRB pWaitingSRB;
 141 PSRB pWaitLast;
 142 PSRB pGoingSRB;
 143 PSRB pGoingLast;
 144 PSRB pActiveSRB;
 145 UCHAR GoingSRBCnt;
 146 UCHAR WaitSRBCnt;/* ??? */
 147 UCHAR DevType;
 148 UCHAR MaxCommand;
 149
 150 /* 0x38: */
 151 ULONG TagMask;
 152
 153 UCHAR UnitSCSIID;/*; SCSI Target ID (SCSI Only) */
 154 UCHAR UnitSCSILUN;/*; SCSI Log. Unit (SCSI Only) */
 155 UCHAR DevMode;
 156 UCHAR IdentifyMsg;
 157
 158 UCHAR CtrlR1;
 159 UCHAR CtrlR3;
 160 UCHAR CtrlR4;
 161
 162 UCHAR DCBFlag;
 163
 164 /* 0x44: */
 165 UCHAR SyncMode;/*; 0:async mode */
 166 UCHAR NegoPeriod;/*;for nego. */
 167 UCHAR SyncPeriod;/*;for reg. */
 168 UCHAR SyncOffset;/*;for reg. and nego.(low nibble) */
 169
 170 /* 0x48:*/
 171 //UCHAR InqDataBuf[8];
 172 //UCHAR CapacityBuf[8];
 173 /* 0x58: */
 174 };
 175
 176 typedefstruct _DCB DC390_DCB, *PDCB;
 177 /*
 178 ;-----------------------------------------------------------------------
 179 ; Adapter Control Block
 180 ;-----------------------------------------------------------------------
 181 */
 182 struct _ACB
 183 {
 184 PSH pScsiHost;
 185 struct _ACB *pNextACB;
 186 USHORT IOPortBase;
 187 UCHAR IRQLevel;
 188 UCHAR status;
 189
 190 UCHAR SRBCount;
 191 UCHAR AdapterIndex;/*; nth Adapter this driver */
 192 UCHAR DeviceCnt;
 193 UCHAR DCBCnt;
 194
 195 /* 0x10: */
 196 UCHAR TagMaxNum;
 197 UCHAR ACBFlag;
 198 UCHAR Gmode2;
 199 UCHAR scan_devices;
 200
 201 PDCB pLinkDCB;
 202 PDCB pLastDCB;
 203 PDCB pDCBRunRobin;
 204 PDCB pActiveDCB;
 205 PSRB pFreeSRB;
 206 PSRB pTmpSRB;
 207
 208 /* 0x2c: */
 209
 210 UCHAR msgin123[4];
 211 UCHAR DCBmap[MAX_SCSI_ID];
 212
 213 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(__SMP__) || DEBUG_SPINLOCKS > 0)
 214 spinlock_t lock;
 215 #endif
 216 UCHAR sel_timeout;
 217 UCHAR glitch_cfg;
 218
 219 UCHAR MsgLen;
 220 UCHAR Ignore_IRQ;/* Not used */
 221
 222 PDEVDECL1;/* Pointer to PCI cfg. space */
 223 /* 0x40/0x3c: */
 224 ULONG Cmds;
 225 ULONG CmdInQ;
 226 ULONG CmdOutOfSRB;
 227 ULONG SelLost;
 228
 229
 230 /* 0x50/0x4c: */
 231 DC390_SRB TmpSRB;
 232 /* 0xb4/0xb0: */
 233 DC390_SRB SRB_array[MAX_SRB_CNT];/* 18 SRBs */
 234 /* 0x7bc/0x7b8: */
 235 };
 236
 237 typedefstruct _ACB DC390_ACB, *PACB;
 238
 239 /*;-----------------------------------------------------------------------*/
 240
 241
 242 #define BIT31 0x80000000
 243 #define BIT30 0x40000000
 244 #define BIT29 0x20000000
 245 #define BIT28 0x10000000
 246 #define BIT27 0x08000000
 247 #define BIT26 0x04000000
 248 #define BIT25 0x02000000
 249 #define BIT24 0x01000000
 250 #define BIT23 0x00800000
 251 #define BIT22 0x00400000
 252 #define BIT21 0x00200000
 253 #define BIT20 0x00100000
 254 #define BIT19 0x00080000
 255 #define BIT18 0x00040000
 256 #define BIT17 0x00020000
 257 #define BIT16 0x00010000
 258 #define BIT15 0x00008000
 259 #define BIT14 0x00004000
 260 #define BIT13 0x00002000
 261 #define BIT12 0x00001000
 262 #define BIT11 0x00000800
 263 #define BIT10 0x00000400
 264 #define BIT9 0x00000200
 265 #define BIT8 0x00000100
 266 #define BIT7 0x00000080
 267 #define BIT6 0x00000040
 268 #define BIT5 0x00000020
 269 #define BIT4 0x00000010
 270 #define BIT3 0x00000008
 271 #define BIT2 0x00000004
 272 #define BIT1 0x00000002
 273 #define BIT0 0x00000001
 274
 275 /*;---UnitCtrlFlag */
 276 #define UNIT_ALLOCATED BIT0
 277 #define UNIT_INFO_CHANGED BIT1
 278 #define FORMATING_MEDIA BIT2
 279 #define UNIT_RETRY BIT3
 280
 281 /*;---UnitFlags */
 282 #define DASD_SUPPORT BIT0
 283 #define SCSI_SUPPORT BIT1
 284 #define ASPI_SUPPORT BIT2
 285
 286 /*;----SRBState machine definition */
 287 #define SRB_FREE 0
 288 #define SRB_WAIT BIT0
 289 #define SRB_READY BIT1
 290 #define SRB_MSGOUT BIT2/*;arbitration+msg_out 1st byte*/
 291 #define SRB_MSGIN BIT3
 292 #define SRB_MSGIN_MULTI BIT4
 293 #define SRB_COMMAND BIT5
 294 #define SRB_START_ BIT6/*;arbitration+msg_out+command_out*/
 295 #define SRB_DISCONNECT BIT7
 296 #define SRB_DATA_XFER BIT8
 297 #define SRB_XFERPAD BIT9
 298 #define SRB_STATUS BIT10
 299 #define SRB_COMPLETED BIT11
 300 #define SRB_ABORT_SENT BIT12
 301 #define DO_SYNC_NEGO BIT13
 302 #define SRB_UNEXPECT_RESEL BIT14
 303
 304 /*;---SRBstatus */
 305 #define SRB_OK BIT0
 306 #define ABORTION BIT1
 307 #define OVER_RUN BIT2
 308 #define UNDER_RUN BIT3
 309 #define PARITY_ERROR BIT4
 310 #define SRB_ERROR BIT5
 311
 312 /*;---ACBFlag */
 313 #define RESET_DEV BIT0
 314 #define RESET_DETECT BIT1
 315 #define RESET_DONE BIT2
 316
 317 /*;---DCBFlag */
 318 #define ABORT_DEV_ BIT0
 319
 320 /*;---SRBFlag */
 321 #define DATAOUT BIT7
 322 #define DATAIN BIT6
 323 #define RESIDUAL_VALID BIT5
 324 #define ENABLE_TIMER BIT4
 325 #define RESET_DEV0 BIT2
 326 #define ABORT_DEV BIT1
 327 #define AUTO_REQSENSE BIT0
 328
 329 /*;---Adapter status */
 330 #define H_STATUS_GOOD 0
 331 #define H_SEL_TIMEOUT 0x11
 332 #define H_OVER_UNDER_RUN 0x12
 333 #define H_UNEXP_BUS_FREE 0x13
 334 #define H_TARGET_PHASE_F 0x14
 335 #define H_INVALID_CCB_OP 0x16
 336 #define H_LINK_CCB_BAD 0x17
 337 #define H_BAD_TARGET_DIR 0x18
 338 #define H_DUPLICATE_CCB 0x19
 339 #define H_BAD_CCB_OR_SG 0x1A
 340 #define H_ABORT 0x0FF
 341
 342 /*; SCSI Status byte codes*//* Twice the values defined in scsi/scsi.h */
 343 #define SCSI_STAT_GOOD 0x0/*; Good status */
 344 #define SCSI_STAT_CHECKCOND 0x02/*; SCSI Check Condition */
 345 #define SCSI_STAT_CONDMET 0x04/*; Condition Met */
 346 #define SCSI_STAT_BUSY 0x08/*; Target busy status */
 347 #define SCSI_STAT_INTER 0x10/*; Intermediate status */
 348 #define SCSI_STAT_INTERCONDMET 0x14/*; Intermediate condition met */
 349 #define SCSI_STAT_RESCONFLICT 0x18/*; Reservation conflict */
 350 #define SCSI_STAT_CMDTERM 0x22/*; Command Terminated */
 351 #define SCSI_STAT_QUEUEFULL 0x28/*; Queue Full */
 352
 353 #define SCSI_STAT_UNEXP_BUS_F 0xFD/*; Unexpect Bus Free */
 354 #define SCSI_STAT_BUS_RST_DETECT 0xFE/*; Scsi Bus Reset detected */
 355 #define SCSI_STAT_SEL_TIMEOUT 0xFF/*; Selection Time out */
 356
 357 /*;---Sync_Mode */
 358 #define SYNC_DISABLE 0
 359 #define SYNC_ENABLE BIT0
 360 #define SYNC_NEGO_DONE BIT1
 361 #define WIDE_ENABLE BIT2/* Not used ;-) */
 362 #define WIDE_NEGO_DONE BIT3/* Not used ;-) */
 363 #define EN_TAG_QUEUEING BIT4
 364 #define EN_ATN_STOP BIT5
 365
 366 #define SYNC_NEGO_OFFSET 15
 367
 368 /*;---SCSI bus phase*/
 369 #define SCSI_DATA_OUT 0
 370 #define SCSI_DATA_IN 1
 371 #define SCSI_COMMAND 2
 372 #define SCSI_STATUS_ 3
 373 #define SCSI_NOP0 4
 374 #define SCSI_NOP1 5
 375 #define SCSI_MSG_OUT 6
 376 #define SCSI_MSG_IN 7
 377
 378 /*;----SCSI MSG BYTE*//* see scsi/scsi.h */
 379 #define MSG_COMPLETE 0x00
 380 #define MSG_EXTENDED 0x01
 381 #define MSG_SAVE_PTR 0x02
 382 #define MSG_RESTORE_PTR 0x03
 383 #define MSG_DISCONNECT 0x04
 384 #define MSG_INITIATOR_ERROR 0x05
 385 #define MSG_ABORT 0x06
 386 #define MSG_REJECT_ 0x07
 387 #define MSG_NOP 0x08
 388 #define MSG_PARITY_ERROR 0x09
 389 #define MSG_LINK_CMD_COMPL 0x0A
 390 #define MSG_LINK_CMD_COMPL_FLG 0x0B
 391 #define MSG_BUS_RESET 0x0C
 392 #define MSG_ABORT_TAG 0x0D
 393 #define MSG_SIMPLE_QTAG 0x20
 394 #define MSG_HEAD_QTAG 0x21
 395 #define MSG_ORDER_QTAG 0x22
 396 #define MSG_IDENTIFY 0x80
 397 #define MSG_HOST_ID 0x0C0
 398
 399 /* cmd->result */
 400 #define STATUS_MASK_ 0xFF
 401 #define MSG_MASK 0xFF00
 402 #define RETURN_MASK 0xFF0000
 403
 404 /*
 405 ** Inquiry Data format
 406 */
 407
 408 typedefstruct _SCSIInqData {/* INQUIRY */
 409
 410  UCHAR DevType;/* Periph Qualifier & Periph Dev Type*/
 411  UCHAR RMB_TypeMod;/* rem media bit & Dev Type Modifier */
 412  UCHAR Vers;/* ISO, ECMA, & ANSI versions */
 413  UCHAR RDF;/* AEN, TRMIOP, & response data format*/
 414  UCHAR AddLen;/* length of additional data */
 415  UCHAR Res1;/* reserved */
 416  UCHAR Res2;/* reserved */
 417  UCHAR Flags;/* RelADr,Wbus32,Wbus16,Sync,etc. */
 418  UCHAR VendorID[8];/* Vendor Identification */
 419  UCHAR ProductID[16];/* Product Identification */
 420  UCHAR ProductRev[4];/* Product Revision */
 421
 422
 423 } SCSI_INQDATA, *PSCSI_INQDATA;
 424
 425
 426 /* Inquiry byte 0 masks */
 427
 428
 429 #define SCSI_DEVTYPE 0x1F/* Peripheral Device Type */
 430 #define SCSI_PERIPHQUAL 0xE0/* Peripheral Qualifier */
 431 #define TYPE_NODEV SCSI_DEVTYPE/* Unknown or no device type */
 432
 433
 434 /* Inquiry byte 1 mask */
 435
 436 #define SCSI_REMOVABLE_MEDIA 0x80/* Removable Media bit (1=removable) */
 437
 438
 439 /* Peripheral Device Type definitions */
 440 /* see include/scsi/scsi.h for the rest */
 441
 442 #define TYPE_PRINTER 0x02/* Printer device */
 443 #define TYPE_COMM 0x09/* Communications device */
 444
 445 /*
 446 ** Inquiry flag definitions (Inq data byte 7)
 447 */
 448
 449 #define SCSI_INQ_RELADR 0x80/* device supports relative addressing*/
 450 #define SCSI_INQ_WBUS32 0x40/* device supports 32 bit data xfers */
 451 #define SCSI_INQ_WBUS16 0x20/* device supports 16 bit data xfers */
 452 #define SCSI_INQ_SYNC 0x10/* device supports synchronous xfer */
 453 #define SCSI_INQ_LINKED 0x08/* device supports linked commands */
 454 #define SCSI_INQ_CMDQUEUE 0x02/* device supports command queueing */
 455 #define SCSI_INQ_SFTRE 0x01/* device supports soft resets */
 456
 457
 458 /*
 459 ;==========================================================
 460 ; EEPROM byte offset
 461 ;==========================================================
 462 */
 463 typedefstruct _EEprom
 464 {
 465 UCHAR EE_MODE1;
 466 UCHAR EE_SPEED;
 467 UCHAR xx1;
 468 UCHAR xx2;
 469 } EEprom, *PEEprom;
 470
 471 #define REAL_EE_ADAPT_SCSI_ID 64
 472 #define REAL_EE_MODE2 65
 473 #define REAL_EE_DELAY 66
 474 #define REAL_EE_TAG_CMD_NUM 67
 475
 476 #define EE_ADAPT_SCSI_ID 32
 477 #define EE_MODE2 33
 478 #define EE_DELAY 34
 479 #define EE_TAG_CMD_NUM 35
 480
 481 #define EE_LEN 40
 482
 483 /*; EE_MODE1 bits definition*/
 484 #define PARITY_CHK_ BIT0
 485 #define SYNC_NEGO_ BIT1
 486 #define EN_DISCONNECT_ BIT2
 487 #define SEND_START_ BIT3
 488 #define TAG_QUEUEING_ BIT4
 489
 490 /*; EE_MODE2 bits definition*/
 491 #define MORE2_DRV BIT0
 492 #define GREATER_1G BIT1
 493 #define RST_SCSI_BUS BIT2
 494 #define ACTIVE_NEGATION BIT3
 495 #define NO_SEEK BIT4
 496 #define LUN_CHECK BIT5
 497
 498 #define ENABLE_CE 1
 499 #define DISABLE_CE 0
 500 #define EEPROM_READ 0x80
 501
 502 /*
 503 ;==========================================================
 504 ; AMD 53C974 Registers bit Definition
 505 ;==========================================================
 506 */
 507 /*
 508 ;====================
 509 ; SCSI Register
 510 ;====================
 511 */
 512
 513 /*; Command Reg.(+0CH) (rw) */
 514 #define DMA_COMMAND BIT7
 515 #define NOP_CMD 0
 516 #define CLEAR_FIFO_CMD 1
 517 #define RST_DEVICE_CMD 2
 518 #define RST_SCSI_BUS_CMD 3
 519
 520 #define INFO_XFER_CMD 0x10
 521 #define INITIATOR_CMD_CMPLTE 0x11
 522 #define MSG_ACCEPTED_CMD 0x12
 523 #define XFER_PAD_BYTE 0x18
 524 #define SET_ATN_CMD 0x1A
 525 #define RESET_ATN_CMD 0x1B
 526
 527 #define SEL_WO_ATN 0x41/* currently not used */
 528 #define SEL_W_ATN 0x42
 529 #define SEL_W_ATN_STOP 0x43
 530 #define SEL_W_ATN3 0x46
 531 #define EN_SEL_RESEL 0x44
 532 #define DIS_SEL_RESEL 0x45/* currently not used */
 533 #define RESEL 0x40/* " */
 534 #define RESEL_ATN3 0x47/* " */
 535
 536 #define DATA_XFER_CMD INFO_XFER_CMD
 537
 538
 539 /*; SCSI Status Reg.(+10H) (r) */
 540 #define INTERRUPT BIT7
 541 #define ILLEGAL_OP_ERR BIT6
 542 #define PARITY_ERR BIT5
 543 #define COUNT_2_ZERO BIT4
 544 #define GROUP_CODE_VALID BIT3
 545 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
 546 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
 547
 548 /*; Interrupt Status Reg.(+14H) (r) */
 549 #define SCSI_RESET BIT7
 550 #define INVALID_CMD BIT6
 551 #define DISCONNECTED BIT5
 552 #define SERVICE_REQUEST BIT4
 553 #define SUCCESSFUL_OP BIT3
 554 #define RESELECTED BIT2
 555 #define SEL_ATTENTION BIT1
 556 #define SELECTED BIT0
 557
 558 /*; Internal State Reg.(+18H) (r) */
 559 #define SYNC_OFFSET_FLAG BIT3
 560 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
 561 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
 562
 563 /*; Clock Factor Reg.(+24H) (w) */
 564 #define CLK_FREQ_40MHZ 0
 565 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
 566 #define CLK_FREQ_30MHZ (BIT2+BIT1)
 567 #define CLK_FREQ_25MHZ (BIT2+BIT0)
 568 #define CLK_FREQ_20MHZ BIT2
 569 #define CLK_FREQ_15MHZ (BIT1+BIT0)
 570 #define CLK_FREQ_10MHZ BIT1
 571
 572 /*; Control Reg. 1(+20H) (rw) */
 573 #define EXTENDED_TIMING BIT7
 574 #define DIS_INT_ON_SCSI_RST BIT6
 575 #define PARITY_ERR_REPO BIT4
 576 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0)/* host adapter ID */
 577
 578 /*; Control Reg. 2(+2CH) (rw) */
 579 #define EN_FEATURE BIT6
 580 #define EN_SCSI2_CMD BIT3
 581
 582 /*; Control Reg. 3(+30H) (rw) */
 583 #define ID_MSG_CHECK BIT7
 584 #define EN_QTAG_MSG BIT6
 585 #define EN_GRP2_CMD BIT5
 586 #define FAST_SCSI BIT4/* ;10MB/SEC */
 587 #define FAST_CLK BIT3/* ;25 - 40 MHZ */
 588
 589 /*; Control Reg. 4(+34H) (rw) */
 590 #define EATER_12NS 0
 591 #define EATER_25NS BIT7
 592 #define EATER_35NS BIT6
 593 #define EATER_0NS (BIT7+BIT6)
 594 #define REDUCED_POWER BIT5
 595 #define CTRL4_RESERVED BIT4/* must be 1 acc. to AM53C974.c */
 596 #define NEGATE_REQACKDATA BIT2
 597 #define NEGATE_REQACK BIT3
 598
 599 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
 600 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
 601
 602 /*
 603 ;====================
 604 ; DMA Register
 605 ;====================
 606 */
 607 /*; DMA Command Reg.(+40H) (rw) */
 608 #define READ_DIRECTION BIT7
 609 #define WRITE_DIRECTION 0
 610 #define EN_DMA_INT BIT6
 611 #define EN_PAGE_INT BIT5/* page transfer interrupt enable */
 612 #define MAP_TO_MDL BIT4
 613 #define DIAGNOSTIC BIT2
 614 #define DMA_IDLE_CMD 0
 615 #define DMA_BLAST_CMD BIT0
 616 #define DMA_ABORT_CMD BIT1
 617 #define DMA_START_CMD (BIT1+BIT0)
 618
 619 /*; DMA Status Reg.(+54H) (r) */
 620 #define PCI_MS_ABORT BIT6
 621 #define BLAST_COMPLETE BIT5
 622 #define SCSI_INTERRUPT BIT4
 623 #define DMA_XFER_DONE BIT3
 624 #define DMA_XFER_ABORT BIT2
 625 #define DMA_XFER_ERROR BIT1
 626 #define POWER_DOWN BIT0
 627
 628 /*; DMA SCSI Bus and Ctrl.(+70H) */
 629 #define EN_INT_ON_PCI_ABORT BIT25
 630 #define WRT_ERASE_DMA_STAT BIT24
 631 #define PW_DOWN_CTRL BIT21
 632 #define SCSI_BUSY BIT20
 633 #define SCLK BIT19
 634 #define SCAM BIT18
 635 #define SCSI_LINES 0x0003ffff
 636
 637 /*
 638 ;==========================================================
 639 ; SCSI Chip register address offset
 640 ;==========================================================
 641 ;Registers are rw unless declared otherwise
 642 */
 643 #define CtcReg_Low 0x00/* r curr. transfer count */
 644 #define CtcReg_Mid 0x04/* r */
 645 #define CtcReg_High 0x38/* r */
 646 #define ScsiFifo 0x08
 647 #define ScsiCmd 0x0C
 648 #define Scsi_Status 0x10/* r */
 649 #define INT_Status 0x14/* r */
 650 #define Sync_Period 0x18/* w */
 651 #define Sync_Offset 0x1C/* w */
 652 #define Clk_Factor 0x24/* w */
 653 #define CtrlReg1 0x20
 654 #define CtrlReg2 0x2C
 655 #define CtrlReg3 0x30
 656 #define CtrlReg4 0x34
 657 #define DMA_Cmd 0x40
 658 #define DMA_XferCnt 0x44/* rw starting transfer count (32 bit) */
 659 #define DMA_XferAddr 0x48/* rw starting physical address (32 bit) */
 660 #define DMA_Wk_ByteCntr 0x4C/* r working byte counter */
 661 #define DMA_Wk_AddrCntr 0x50/* r working address counter */
 662 #define DMA_Status 0x54/* r */
 663 #define DMA_MDL_Addr 0x58/* rw starting MDL address */
 664 #define DMA_Wk_MDL_Cntr 0x5C/* r working MDL counter */
 665 #define DMA_ScsiBusCtrl 0x70/* rw SCSI Bus, PCI/DMA Ctrl */
 666
 667 #define StcReg_Low CtcReg_Low/* w start transfer count */
 668 #define StcReg_Mid CtcReg_Mid/* w */
 669 #define StcReg_High CtcReg_High/* w */
 670 #define Scsi_Dest_ID Scsi_Status/* w */
 671 #define Scsi_TimeOut INT_Status/* w */
 672 #define Intern_State Sync_Period/* r */
 673 #define Current_Fifo Sync_Offset/* r Curr. FIFO / int. state */
 674
 675
 676 #define DC390_read8(address) \
 677  (inb (pACB->IOPortBase + (address)))
 678
 679 #define DC390_read8_(address, base) \
 680  (inb ((USHORT)(base) + (address)))
 681
 682 #define DC390_read16(address) \
 683  (inw (pACB->IOPortBase + (address)))
 684
 685 #define DC390_read32(address) \
 686  (inl (pACB->IOPortBase + (address)))
 687
 688 #define DC390_write8(address,value) \
 689  outb ((value), pACB->IOPortBase + (address))
 690
 691 #define DC390_write8_(address,value,base) \
 692  outb ((value), (USHORT)(base) + (address))
 693
 694 #define DC390_write16(address,value) \
 695  outw ((value), pACB->IOPortBase + (address))
 696
 697 #define DC390_write32(address,value) \
 698  outl ((value), pACB->IOPortBase + (address))
 699
 700
 701 #endif/* _TMSCSIM_H */