drivers/scsi/tmscsim.h

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 1 /***********************************************************************
 2 ;* File Name : TMSCSIM.H *
 3 ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter *
 4 ;* Device Driver *
 5 ;***********************************************************************/
 6 /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */
 7
 8 #ifndef _TMSCSIM_H
 9 #define _TMSCSIM_H
 10
 11 #include <linux/types.h>
 12 #include <linux/config.h>
 13 /* 2.0 compat */
 14 #if defined(__SMP__) && !defined(CONFIG_SMP)
 15 # if LINUX_VERSION_CODE < KERNEL_VERSION (2,2,0)
 16 # define CONFIG_SMP
 17 # else
 18 # error __SMP__ defined but not CONFIG_SMP
 19 # endif
 20 #endif
 21
 22
 23 #define IRQ_NONE 255
 24
 25 #define MAX_ADAPTER_NUM 4
 26 #define MAX_SG_LIST_BUF 16/* Not used */
 27 #define MAX_CMD_PER_LUN 32
 28 #define MAX_CMD_QUEUE MAX_CMD_PER_LUN+MAX_CMD_PER_LUN/2+1
 29 #define MAX_SCSI_ID 8
 30 #define MAX_SRB_CNT MAX_CMD_QUEUE+1/* Max number of started commands */
 31
 32 #define SEL_TIMEOUT 153/* 250 ms selection timeout (@ 40 MHz) */
 33
 34 #define END_SCAN 2
 35
 36 typedef u8 UCHAR;/* 8 bits */
 37 typedef u16 USHORT;/* 16 bits */
 38 typedef u32 UINT;/* 32 bits */
 39 typedefunsigned long ULONG;/* 32/64 bits */
 40
 41 typedef UCHAR *PUCHAR;
 42 typedef USHORT *PUSHORT;
 43 typedef UINT *PUINT;
 44 typedef ULONG *PULONG;
 45 typedef Scsi_Host_Template *PSHT;
 46 typedefstruct Scsi_Host *PSH;
 47 typedef Scsi_Device *PSCSIDEV;
 48 typedef Scsi_Cmnd *PSCSICMD;
 49 typedefvoid*PVOID;
 50 typedefstruct scatterlist *PSGL, SGL;
 51
 52
 53 /*;-----------------------------------------------------------------------*/
 54 typedefstruct _SyncMsg
 55 {
 56 UCHAR ExtendMsg;
 57 UCHAR ExtMsgLen;
 58 UCHAR SyncXferReq;
 59 UCHAR Period;
 60 UCHAR ReqOffset;
 61 } SyncMsg;
 62 /*;-----------------------------------------------------------------------*/
 63 typedefstruct _Capacity
 64 {
 65 ULONG BlockCount;
 66 ULONG BlockLength;
 67 } Capacity;
 68 /*;-----------------------------------------------------------------------*/
 69 typedefstruct _SGentry
 70 {
 71 ULONG SGXferDataPtr;
 72 ULONG SGXferDataLen;
 73 } SGentry;
 74
 75 typedefstruct _SGentry1
 76 {
 77 ULONG SGXLen;
 78 ULONG SGXPtr;
 79 } SGentry1, *PSGE;
 80
 81
 82 /*
 83 ;-----------------------------------------------------------------------
 84 ; SCSI Request Block
 85 ;-----------------------------------------------------------------------
 86 */
 87 struct _SRB
 88 {
 89 //UCHAR CmdBlock[12];
 90
 91 struct _SRB *pNextSRB;
 92 struct _DCB *pSRBDCB;
 93 PSCSICMD pcmd;
 94 PSGL pSegmentList;
 95
 96 /* 0x10: */
 97 SGL Segmentx;/* make a one entry of S/G list table */
 98
 99 /* 0x1c: */
 100 ULONG SGBusAddr;/*;a segment starting address as seen by AM53C974A*/
 101 ULONG SGToBeXferLen;/*; to be xfer length */
 102 ULONG TotalXferredLen;
 103 ULONG SavedTotXLen;
 104 UINT SRBState;
 105
 106 /* 0x30: */
 107 UCHAR SRBStatus;
 108 UCHAR SRBFlag;/*; b0-AutoReqSense,b6-Read,b7-write */
 109 /*; b4-settimeout,b5-Residual valid */
 110 UCHAR AdaptStatus;
 111 UCHAR TargetStatus;
 112
 113 UCHAR ScsiPhase;
 114 UCHAR TagNumber;
 115 UCHAR SGIndex;
 116 UCHAR SGcount;
 117
 118 /* 0x38: */
 119 UCHAR MsgCnt;
 120 UCHAR EndMessage;
 121 UCHAR RetryCnt;
 122 UCHAR SavedSGCount;
 123
 124 ULONG Saved_Ptr;
 125
 126 /* 0x40: */
 127 UCHAR MsgInBuf[6];
 128 UCHAR MsgOutBuf[6];
 129
 130 //UCHAR IORBFlag; /*;81h-Reset, 2-retry */
 131 /* 0x4c: */
 132 };
 133
 134
 135 typedefstruct _SRB DC390_SRB, *PSRB;
 136
 137 /*
 138 ;-----------------------------------------------------------------------
 139 ; Device Control Block
 140 ;-----------------------------------------------------------------------
 141 */
 142 struct _DCB
 143 {
 144 struct _DCB *pNextDCB;
 145 struct _ACB *pDCBACB;
 146
 147 /* Aborted Commands */
 148 //PSCSICMD AboIORBhead;
 149 //PSCSICMD AboIORBtail;
 150 //ULONG AboIORBcnt;
 151
 152 /* 0x08: */
 153 /* Queued SRBs */
 154 PSRB pWaitingSRB;
 155 PSRB pWaitLast;
 156 PSRB pGoingSRB;
 157 PSRB pGoingLast;
 158 PSRB pActiveSRB;
 159 UCHAR WaitSRBCnt;/* Not used */
 160 UCHAR GoingSRBCnt;
 161
 162 UCHAR DevType;
 163 UCHAR MaxCommand;
 164
 165 /* 0x20: */
 166 UINT TagMask;
 167
 168 UCHAR TargetID;/*; SCSI Target ID (SCSI Only) */
 169 UCHAR TargetLUN;/*; SCSI Log. Unit (SCSI Only) */
 170 UCHAR DevMode;
 171 UCHAR DCBFlag;
 172
 173 UCHAR CtrlR1;
 174 UCHAR CtrlR3;
 175 UCHAR CtrlR4;
 176 UCHAR Inquiry7;
 177
 178 /* 0x2c: */
 179 UCHAR SyncMode;/*; 0:async mode */
 180 UCHAR NegoPeriod;/*;for nego. */
 181 UCHAR SyncPeriod;/*;for reg. */
 182 UCHAR SyncOffset;/*;for reg. and nego.(low nibble) */
 183
 184 /* 0x30:*/
 185 //UCHAR InqDataBuf[8];
 186 //UCHAR CapacityBuf[8];
 187 ///* 0x40: */
 188 };
 189
 190 typedefstruct _DCB DC390_DCB, *PDCB;
 191 /*
 192 ;-----------------------------------------------------------------------
 193 ; Adapter Control Block
 194 ;-----------------------------------------------------------------------
 195 */
 196 struct _ACB
 197 {
 198 PSH pScsiHost;
 199 struct _ACB *pNextACB;
 200 USHORT IOPortBase;
 201 UCHAR IRQLevel;
 202 UCHAR status;
 203
 204 UCHAR SRBCount;
 205 UCHAR AdapterIndex;/*; nth Adapter this driver */
 206 UCHAR DeviceCnt;
 207 UCHAR DCBCnt;
 208
 209 /* 0x10: */
 210 UCHAR TagMaxNum;
 211 UCHAR ACBFlag;
 212 UCHAR Gmode2;
 213 UCHAR scan_devices;
 214
 215 PDCB pLinkDCB;
 216 PDCB pLastDCB;
 217 PDCB pDCBRunRobin;
 218
 219 PDCB pActiveDCB;
 220 PSRB pFreeSRB;
 221 PSRB pTmpSRB;
 222
 223 /* 0x2c: */
 224 ULONG QueryCnt;
 225 PSCSICMD pQueryHead;
 226 PSCSICMD pQueryTail;
 227
 228 /* 0x38: */
 229 UCHAR msgin123[4];
 230 UCHAR DCBmap[MAX_SCSI_ID];
 231 UCHAR Connected;
 232 UCHAR pad;
 233
 234 /* 0x3c: */
 235 #if defined(USE_SPINLOCKS) && USE_SPINLOCKS > 1 && (defined(CONFIG_SMP) || DEBUG_SPINLOCKS > 0)
 236 spinlock_t lock;
 237 #endif
 238 UCHAR sel_timeout;
 239 UCHAR glitch_cfg;
 240
 241 UCHAR MsgLen;
 242 UCHAR Ignore_IRQ;/* Not used */
 243
 244 PDEVDECL1;/* Pointer to PCI cfg. space */
 245 /* 0x4c/0x48: */
 246 ULONG Cmds;
 247 UINT SelLost;
 248 UINT SelConn;
 249 UINT CmdInQ;
 250 UINT CmdOutOfSRB;
 251
 252 /* 0x60/0x5c: */
 253 struct timer_list Waiting_Timer;
 254 /* 0x74/0x70: */
 255 DC390_SRB TmpSRB;
 256 /* 0xd8/0xd4: */
 257 DC390_SRB SRB_array[MAX_SRB_CNT];/* 50 SRBs */
 258 /* 0xfb0/0xfac: */
 259 };
 260
 261 typedefstruct _ACB DC390_ACB, *PACB;
 262
 263 /*;-----------------------------------------------------------------------*/
 264
 265
 266 #define BIT31 0x80000000
 267 #define BIT30 0x40000000
 268 #define BIT29 0x20000000
 269 #define BIT28 0x10000000
 270 #define BIT27 0x08000000
 271 #define BIT26 0x04000000
 272 #define BIT25 0x02000000
 273 #define BIT24 0x01000000
 274 #define BIT23 0x00800000
 275 #define BIT22 0x00400000
 276 #define BIT21 0x00200000
 277 #define BIT20 0x00100000
 278 #define BIT19 0x00080000
 279 #define BIT18 0x00040000
 280 #define BIT17 0x00020000
 281 #define BIT16 0x00010000
 282 #define BIT15 0x00008000
 283 #define BIT14 0x00004000
 284 #define BIT13 0x00002000
 285 #define BIT12 0x00001000
 286 #define BIT11 0x00000800
 287 #define BIT10 0x00000400
 288 #define BIT9 0x00000200
 289 #define BIT8 0x00000100
 290 #define BIT7 0x00000080
 291 #define BIT6 0x00000040
 292 #define BIT5 0x00000020
 293 #define BIT4 0x00000010
 294 #define BIT3 0x00000008
 295 #define BIT2 0x00000004
 296 #define BIT1 0x00000002
 297 #define BIT0 0x00000001
 298
 299 /*;---UnitCtrlFlag */
 300 #define UNIT_ALLOCATED BIT0
 301 #define UNIT_INFO_CHANGED BIT1
 302 #define FORMATING_MEDIA BIT2
 303 #define UNIT_RETRY BIT3
 304
 305 /*;---UnitFlags */
 306 #define DASD_SUPPORT BIT0
 307 #define SCSI_SUPPORT BIT1
 308 #define ASPI_SUPPORT BIT2
 309
 310 /*;----SRBState machine definition */
 311 #define SRB_FREE 0
 312 #define SRB_WAIT BIT0
 313 #define SRB_READY BIT1
 314 #define SRB_MSGOUT BIT2/*;arbitration+msg_out 1st byte*/
 315 #define SRB_MSGIN BIT3
 316 #define SRB_MSGIN_MULTI BIT4
 317 #define SRB_COMMAND BIT5
 318 #define SRB_START_ BIT6/*;arbitration+msg_out+command_out*/
 319 #define SRB_DISCONNECT BIT7
 320 #define SRB_DATA_XFER BIT8
 321 #define SRB_XFERPAD BIT9
 322 #define SRB_STATUS BIT10
 323 #define SRB_COMPLETED BIT11
 324 #define SRB_ABORT_SENT BIT12
 325 #define DO_SYNC_NEGO BIT13
 326 #define SRB_UNEXPECT_RESEL BIT14
 327
 328 /*;---SRBstatus */
 329 #define SRB_OK BIT0
 330 #define ABORTION BIT1
 331 #define OVER_RUN BIT2
 332 #define UNDER_RUN BIT3
 333 #define PARITY_ERROR BIT4
 334 #define SRB_ERROR BIT5
 335
 336 /*;---ACBFlag */
 337 #define RESET_DEV BIT0
 338 #define RESET_DETECT BIT1
 339 #define RESET_DONE BIT2
 340
 341 /*;---DCBFlag */
 342 #define ABORT_DEV_ BIT0
 343
 344 /*;---SRBFlag */
 345 #define DATAOUT BIT7
 346 #define DATAIN BIT6
 347 #define RESIDUAL_VALID BIT5
 348 #define ENABLE_TIMER BIT4
 349 #define RESET_DEV0 BIT2
 350 #define ABORT_DEV BIT1
 351 #define AUTO_REQSENSE BIT0
 352
 353 /*;---Adapter status */
 354 #define H_STATUS_GOOD 0
 355 #define H_SEL_TIMEOUT 0x11
 356 #define H_OVER_UNDER_RUN 0x12
 357 #define H_UNEXP_BUS_FREE 0x13
 358 #define H_TARGET_PHASE_F 0x14
 359 #define H_INVALID_CCB_OP 0x16
 360 #define H_LINK_CCB_BAD 0x17
 361 #define H_BAD_TARGET_DIR 0x18
 362 #define H_DUPLICATE_CCB 0x19
 363 #define H_BAD_CCB_OR_SG 0x1A
 364 #define H_ABORT 0x0FF
 365
 366 /*; SCSI Status byte codes*/
 367 /* The values defined in include/scsi/scsi.h, to be shifted << 1 */
 368
 369 #define SCSI_STAT_UNEXP_BUS_F 0xFD/*; Unexpect Bus Free */
 370 #define SCSI_STAT_BUS_RST_DETECT 0xFE/*; Scsi Bus Reset detected */
 371 #define SCSI_STAT_SEL_TIMEOUT 0xFF/*; Selection Time out */
 372
 373 /* cmd->result */
 374 #define RES_TARGET 0x000000FF/* Target State */
 375 #define RES_TARGET_LNX STATUS_MASK/* Only official ... */
 376 #define RES_ENDMSG 0x0000FF00/* End Message */
 377 #define RES_DID 0x00FF0000/* DID_ codes */
 378 #define RES_DRV 0xFF000000/* DRIVER_ codes */
 379
 380 #define MK_RES(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt))
 381 #define MK_RES_LNX(drv,did,msg,tgt) ((int)(drv)<<24 | (int)(did)<<16 | (int)(msg)<<8 | (int)(tgt)<<1)
 382
 383 #define SET_RES_TARGET(who,tgt) { who &= ~RES_TARGET; who |= (int)(tgt); }
 384 #define SET_RES_TARGET_LNX(who,tgt) { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; }
 385 #define SET_RES_MSG(who,msg) { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; }
 386 #define SET_RES_DID(who,did) { who &= ~RES_DID; who |= (int)(did) << 16; }
 387 #define SET_RES_DRV(who,drv) { who &= ~RES_DRV; who |= (int)(drv) << 24; }
 388
 389 /*;---Sync_Mode */
 390 #define SYNC_DISABLE 0
 391 #define SYNC_ENABLE BIT0
 392 #define SYNC_NEGO_DONE BIT1
 393 #define WIDE_ENABLE BIT2/* Not used ;-) */
 394 #define WIDE_NEGO_DONE BIT3/* Not used ;-) */
 395 #define EN_TAG_QUEUEING BIT4
 396 #define EN_ATN_STOP BIT5
 397
 398 #define SYNC_NEGO_OFFSET 15
 399
 400 /*;---SCSI bus phase*/
 401 #define SCSI_DATA_OUT 0
 402 #define SCSI_DATA_IN 1
 403 #define SCSI_COMMAND 2
 404 #define SCSI_STATUS_ 3
 405 #define SCSI_NOP0 4
 406 #define SCSI_NOP1 5
 407 #define SCSI_MSG_OUT 6
 408 #define SCSI_MSG_IN 7
 409
 410 /*;----SCSI MSG BYTE*//* see scsi/scsi.h *//* One is missing ! */
 411 #define ABORT_TAG 0x0d
 412
 413 /*
 414 ** Inquiry Data format
 415 */
 416
 417 typedefstruct _SCSIInqData {/* INQUIRY */
 418
 419  UCHAR DevType;/* Periph Qualifier & Periph Dev Type*/
 420  UCHAR RMB_TypeMod;/* rem media bit & Dev Type Modifier */
 421  UCHAR Vers;/* ISO, ECMA, & ANSI versions */
 422  UCHAR RDF;/* AEN, TRMIOP, & response data format*/
 423  UCHAR AddLen;/* length of additional data */
 424  UCHAR Res1;/* reserved */
 425  UCHAR Res2;/* reserved */
 426  UCHAR Flags;/* RelADr,Wbus32,Wbus16,Sync,etc. */
 427  UCHAR VendorID[8];/* Vendor Identification */
 428  UCHAR ProductID[16];/* Product Identification */
 429  UCHAR ProductRev[4];/* Product Revision */
 430
 431
 432 } SCSI_INQDATA, *PSCSI_INQDATA;
 433
 434
 435 /* Inquiry byte 0 masks */
 436
 437
 438 #define SCSI_DEVTYPE 0x1F/* Peripheral Device Type */
 439 #define SCSI_PERIPHQUAL 0xE0/* Peripheral Qualifier */
 440 #define TYPE_NODEV SCSI_DEVTYPE/* Unknown or no device type */
 441
 442
 443 /* Inquiry byte 1 mask */
 444
 445 #define SCSI_REMOVABLE_MEDIA 0x80/* Removable Media bit (1=removable) */
 446
 447
 448 /* Peripheral Device Type definitions */
 449 /* see include/scsi/scsi.h for the rest */
 450
 451 #ifndef TYPE_PRINTER
 452 # define TYPE_PRINTER 0x02/* Printer device */
 453 #endif
 454 #ifndef TYPE_COMM
 455 # define TYPE_COMM 0x09/* Communications device */
 456 #endif
 457
 458 /*
 459 ** Inquiry flag definitions (Inq data byte 7)
 460 */
 461
 462 #define SCSI_INQ_RELADR 0x80/* device supports relative addressing*/
 463 #define SCSI_INQ_WBUS32 0x40/* device supports 32 bit data xfers */
 464 #define SCSI_INQ_WBUS16 0x20/* device supports 16 bit data xfers */
 465 #define SCSI_INQ_SYNC 0x10/* device supports synchronous xfer */
 466 #define SCSI_INQ_LINKED 0x08/* device supports linked commands */
 467 #define SCSI_INQ_CMDQUEUE 0x02/* device supports command queueing */
 468 #define SCSI_INQ_SFTRE 0x01/* device supports soft resets */
 469
 470
 471 /*
 472 ;==========================================================
 473 ; EEPROM byte offset
 474 ;==========================================================
 475 */
 476 typedefstruct _EEprom
 477 {
 478 UCHAR EE_MODE1;
 479 UCHAR EE_SPEED;
 480 UCHAR xx1;
 481 UCHAR xx2;
 482 } EEprom, *PEEprom;
 483
 484 #define REAL_EE_ADAPT_SCSI_ID 64
 485 #define REAL_EE_MODE2 65
 486 #define REAL_EE_DELAY 66
 487 #define REAL_EE_TAG_CMD_NUM 67
 488
 489 #define EE_ADAPT_SCSI_ID 32
 490 #define EE_MODE2 33
 491 #define EE_DELAY 34
 492 #define EE_TAG_CMD_NUM 35
 493
 494 #define EE_LEN 40
 495
 496 /*; EE_MODE1 bits definition*/
 497 #define PARITY_CHK_ BIT0
 498 #define SYNC_NEGO_ BIT1
 499 #define EN_DISCONNECT_ BIT2
 500 #define SEND_START_ BIT3
 501 #define TAG_QUEUEING_ BIT4
 502
 503 /*; EE_MODE2 bits definition*/
 504 #define MORE2_DRV BIT0
 505 #define GREATER_1G BIT1
 506 #define RST_SCSI_BUS BIT2
 507 #define ACTIVE_NEGATION BIT3
 508 #define NO_SEEK BIT4
 509 #define LUN_CHECK BIT5
 510
 511 #define ENABLE_CE 1
 512 #define DISABLE_CE 0
 513 #define EEPROM_READ 0x80
 514
 515 /*
 516 ;==========================================================
 517 ; AMD 53C974 Registers bit Definition
 518 ;==========================================================
 519 */
 520 /*
 521 ;====================
 522 ; SCSI Register
 523 ;====================
 524 */
 525
 526 /*; Command Reg.(+0CH) (rw) */
 527 #define DMA_COMMAND BIT7
 528 #define NOP_CMD 0
 529 #define CLEAR_FIFO_CMD 1
 530 #define RST_DEVICE_CMD 2
 531 #define RST_SCSI_BUS_CMD 3
 532
 533 #define INFO_XFER_CMD 0x10
 534 #define INITIATOR_CMD_CMPLTE 0x11
 535 #define MSG_ACCEPTED_CMD 0x12
 536 #define XFER_PAD_BYTE 0x18
 537 #define SET_ATN_CMD 0x1A
 538 #define RESET_ATN_CMD 0x1B
 539
 540 #define SEL_WO_ATN 0x41/* currently not used */
 541 #define SEL_W_ATN 0x42
 542 #define SEL_W_ATN_STOP 0x43
 543 #define SEL_W_ATN3 0x46
 544 #define EN_SEL_RESEL 0x44
 545 #define DIS_SEL_RESEL 0x45/* currently not used */
 546 #define RESEL 0x40/* " */
 547 #define RESEL_ATN3 0x47/* " */
 548
 549 #define DATA_XFER_CMD INFO_XFER_CMD
 550
 551
 552 /*; SCSI Status Reg.(+10H) (r) */
 553 #define INTERRUPT BIT7
 554 #define ILLEGAL_OP_ERR BIT6
 555 #define PARITY_ERR BIT5
 556 #define COUNT_2_ZERO BIT4
 557 #define GROUP_CODE_VALID BIT3
 558 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0)
 559 /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */
 560
 561 /*; Interrupt Status Reg.(+14H) (r) */
 562 #define SCSI_RESET BIT7
 563 #define INVALID_CMD BIT6
 564 #define DISCONNECTED BIT5
 565 #define SERVICE_REQUEST BIT4
 566 #define SUCCESSFUL_OP BIT3
 567 #define RESELECTED BIT2
 568 #define SEL_ATTENTION BIT1
 569 #define SELECTED BIT0
 570
 571 /*; Internal State Reg.(+18H) (r) */
 572 #define SYNC_OFFSET_FLAG BIT3
 573 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0)
 574 /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */
 575
 576 /*; Clock Factor Reg.(+24H) (w) */
 577 #define CLK_FREQ_40MHZ 0
 578 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0)
 579 #define CLK_FREQ_30MHZ (BIT2+BIT1)
 580 #define CLK_FREQ_25MHZ (BIT2+BIT0)
 581 #define CLK_FREQ_20MHZ BIT2
 582 #define CLK_FREQ_15MHZ (BIT1+BIT0)
 583 #define CLK_FREQ_10MHZ BIT1
 584
 585 /*; Control Reg. 1(+20H) (rw) */
 586 #define EXTENDED_TIMING BIT7
 587 #define DIS_INT_ON_SCSI_RST BIT6
 588 #define PARITY_ERR_REPO BIT4
 589 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0)/* host adapter ID */
 590
 591 /*; Control Reg. 2(+2CH) (rw) */
 592 #define EN_FEATURE BIT6
 593 #define EN_SCSI2_CMD BIT3
 594
 595 /*; Control Reg. 3(+30H) (rw) */
 596 #define ID_MSG_CHECK BIT7
 597 #define EN_QTAG_MSG BIT6
 598 #define EN_GRP2_CMD BIT5
 599 #define FAST_SCSI BIT4/* ;10MB/SEC */
 600 #define FAST_CLK BIT3/* ;25 - 40 MHZ */
 601
 602 /*; Control Reg. 4(+34H) (rw) */
 603 #define EATER_12NS 0
 604 #define EATER_25NS BIT7
 605 #define EATER_35NS BIT6
 606 #define EATER_0NS (BIT7+BIT6)
 607 #define REDUCED_POWER BIT5
 608 #define CTRL4_RESERVED BIT4/* must be 1 acc. to AM53C974.c */
 609 #define NEGATE_REQACKDATA BIT2
 610 #define NEGATE_REQACK BIT3
 611
 612 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2)))
 613 #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0)
 614
 615 /*
 616 ;====================
 617 ; DMA Register
 618 ;====================
 619 */
 620 /*; DMA Command Reg.(+40H) (rw) */
 621 #define READ_DIRECTION BIT7
 622 #define WRITE_DIRECTION 0
 623 #define EN_DMA_INT BIT6
 624 #define EN_PAGE_INT BIT5/* page transfer interrupt enable */
 625 #define MAP_TO_MDL BIT4
 626 #define DIAGNOSTIC BIT2
 627 #define DMA_IDLE_CMD 0
 628 #define DMA_BLAST_CMD BIT0
 629 #define DMA_ABORT_CMD BIT1
 630 #define DMA_START_CMD (BIT1+BIT0)
 631
 632 /*; DMA Status Reg.(+54H) (r) */
 633 #define PCI_MS_ABORT BIT6
 634 #define BLAST_COMPLETE BIT5
 635 #define SCSI_INTERRUPT BIT4
 636 #define DMA_XFER_DONE BIT3
 637 #define DMA_XFER_ABORT BIT2
 638 #define DMA_XFER_ERROR BIT1
 639 #define POWER_DOWN BIT0
 640
 641 /*; DMA SCSI Bus and Ctrl.(+70H) */
 642 #define EN_INT_ON_PCI_ABORT BIT25
 643 #define WRT_ERASE_DMA_STAT BIT24
 644 #define PW_DOWN_CTRL BIT21
 645 #define SCSI_BUSY BIT20
 646 #define SCLK BIT19
 647 #define SCAM BIT18
 648 #define SCSI_LINES 0x0003ffff
 649
 650 /*
 651 ;==========================================================
 652 ; SCSI Chip register address offset
 653 ;==========================================================
 654 ;Registers are rw unless declared otherwise
 655 */
 656 #define CtcReg_Low 0x00/* r curr. transfer count */
 657 #define CtcReg_Mid 0x04/* r */
 658 #define CtcReg_High 0x38/* r */
 659 #define ScsiFifo 0x08
 660 #define ScsiCmd 0x0C
 661 #define Scsi_Status 0x10/* r */
 662 #define INT_Status 0x14/* r */
 663 #define Sync_Period 0x18/* w */
 664 #define Sync_Offset 0x1C/* w */
 665 #define Clk_Factor 0x24/* w */
 666 #define CtrlReg1 0x20
 667 #define CtrlReg2 0x2C
 668 #define CtrlReg3 0x30
 669 #define CtrlReg4 0x34
 670 #define DMA_Cmd 0x40
 671 #define DMA_XferCnt 0x44/* rw starting transfer count (32 bit) */
 672 #define DMA_XferAddr 0x48/* rw starting physical address (32 bit) */
 673 #define DMA_Wk_ByteCntr 0x4C/* r working byte counter */
 674 #define DMA_Wk_AddrCntr 0x50/* r working address counter */
 675 #define DMA_Status 0x54/* r */
 676 #define DMA_MDL_Addr 0x58/* rw starting MDL address */
 677 #define DMA_Wk_MDL_Cntr 0x5C/* r working MDL counter */
 678 #define DMA_ScsiBusCtrl 0x70/* rw SCSI Bus, PCI/DMA Ctrl */
 679
 680 #define StcReg_Low CtcReg_Low/* w start transfer count */
 681 #define StcReg_Mid CtcReg_Mid/* w */
 682 #define StcReg_High CtcReg_High/* w */
 683 #define Scsi_Dest_ID Scsi_Status/* w */
 684 #define Scsi_TimeOut INT_Status/* w */
 685 #define Intern_State Sync_Period/* r */
 686 #define Current_Fifo Sync_Offset/* r Curr. FIFO / int. state */
 687
 688
 689 #define DC390_read8(address) \
 690  (inb (pACB->IOPortBase + (address)))
 691
 692 #define DC390_read8_(address, base) \
 693  (inb ((USHORT)(base) + (address)))
 694
 695 #define DC390_read16(address) \
 696  (inw (pACB->IOPortBase + (address)))
 697
 698 #define DC390_read32(address) \
 699  (inl (pACB->IOPortBase + (address)))
 700
 701 #define DC390_write8(address,value) \
 702  outb ((value), pACB->IOPortBase + (address))
 703
 704 #define DC390_write8_(address,value,base) \
 705  outb ((value), (USHORT)(base) + (address))
 706
 707 #define DC390_write16(address,value) \
 708  outw ((value), pACB->IOPortBase + (address))
 709
 710 #define DC390_write32(address,value) \
 711  outl ((value), pACB->IOPortBase + (address))
 712
 713
 714 #endif/* _TMSCSIM_H */