drivers/sound/sonicvibes.c

Name: Public Git Hosting - davej-history.git/blob - drivers/sound/sonicvibes.c
Rating: 4.4 (9856 reviews)
 1 /*****************************************************************************/
 2
 3 /*
 4  * sonicvibes.c -- S3 Sonic Vibes audio driver.
 5  *
 6  * Copyright (C) 1998-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
 7  *
 8  * This program is free software; you can redistribute it and/or modify
 9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  *
 22  * Special thanks to David C. Niemi
 23  *
 24  *
 25  * Module command line parameters:
 26  * none so far
 27  *
 28  *
 29  * Supported devices:
 30  * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
 31  * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
 32  * /dev/midi simple MIDI UART interface, no ioctl
 33  *
 34  * The card has both an FM and a Wavetable synth, but I have to figure
 35  * out first how to drive them...
 36  *
 37  * Revision history
 38  * 06.05.1998 0.1 Initial release
 39  * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
 40  * First stab at a simple midi interface (no bells&whistles)
 41  * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
 42  * set_dac_rate in the FMODE_WRITE case in sv_open
 43  * Fix hwptr out of bounds (now mpg123 works)
 44  * 14.05.1998 0.4 Don't allow excessive interrupt rates
 45  * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
 46  * 03.08.1998 0.6 Do not include modversions.h
 47  * Now mixer behaviour can basically be selected between
 48  * "OSS documented" and "OSS actual" behaviour
 49  * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
 50  * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
 51  * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
 52  * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
 53  * hopefully killed the egcs section type conflict
 54  * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
 55  * reported by Johan Maes <joma@telindus.be>
 56  * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
 57  * read/write cannot be executed
 58  * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
 59  * lockups of the sound chip and revive it. This is basically
 60  * an ugly hack, but at least applications using this driver
 61  * won't hang forever. I don't know why these lockups happen,
 62  * it might well be the motherboard chipset (an early 486 PCI
 63  * board with ALI chipset), since every busmastering 100MB
 64  * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
 65  * exhibit similar behaviour (they work for a couple of packets
 66  * and then lock up and can be revived by ifconfig down/up).
 67  * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
 68  * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
 69  * Alpha fixes reported by Peter Jones <pjones@redhat.com>
 70  * Note: dmaio hack might still be wrong on archs other than i386
 71  * 15.06.1999 0.15 Fix bad allocation bug.
 72  * Thanks to Deti Fliegl <fliegl@in.tum.de>
 73  * 28.06.1999 0.16 Add pci_set_master
 74  * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
 75  * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
 76  * 12.08.1999 0.18 module_init/__setup fixes
 77  * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
 78  * 31.08.1999 0.20 add spin_lock_init
 79  * use new resource allocation to allocate DDMA IO space
 80  * replaced current->state = x with set_current_state(x)
 81  * 03.09.1999 0.21 change read semantics for MIDI to match
 82  * OSS more closely; remove possible wakeup race
 83  * 28.10.1999 0.22 More waitqueue races fixed
 84  * 01.12.1999 0.23 New argument to allocate_resource
 85  * 07.12.1999 0.24 More allocate_resource semantics change
 86  * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
 87  * Tim Janik's BSE (Bedevilled Sound Engine) found this
 88  * use Martin Mares' pci_assign_resource
 89  * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
 90  * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
 91  *
 92  */
 93
 94 /*****************************************************************************/
 95
 96 #include <linux/version.h>
 97 #include <linux/module.h>
 98 #include <linux/string.h>
 99 #include <linux/ioport.h>
 100 #include <linux/sched.h>
 101 #include <linux/delay.h>
 102 #include <linux/sound.h>
 103 #include <linux/malloc.h>
 104 #include <linux/soundcard.h>
 105 #include <linux/pci.h>
 106 #include <asm/io.h>
 107 #include <asm/dma.h>
 108 #include <linux/init.h>
 109 #include <linux/poll.h>
 110 #include <linux/spinlock.h>
 111 #include <linux/smp_lock.h>
 112 #include <linux/wrapper.h>
 113 #include <asm/uaccess.h>
 114 #include <asm/hardirq.h>
 115
 116 #include"dm.h"
 117
 118 /* --------------------------------------------------------------------- */
 119
 120 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 121
 122 /* --------------------------------------------------------------------- */
 123
 124 #ifndef PCI_VENDOR_ID_S3
 125 #define PCI_VENDOR_ID_S3 0x5333
 126 #endif
 127 #ifndef PCI_DEVICE_ID_S3_SONICVIBES
 128 #define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
 129 #endif
 130
 131 #define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
 132
 133 #define SV_EXTENT_SB 0x10
 134 #define SV_EXTENT_ENH 0x10
 135 #define SV_EXTENT_SYNTH 0x4
 136 #define SV_EXTENT_MIDI 0x4
 137 #define SV_EXTENT_GAME 0x8
 138 #define SV_EXTENT_DMA 0x10
 139
 140 /*
 141  * we are not a bridge and thus use a resource for DDMA that is used for bridges but
 142  * left empty for normal devices
 143  */
 144 #define RESOURCE_SB 0
 145 #define RESOURCE_ENH 1
 146 #define RESOURCE_SYNTH 2
 147 #define RESOURCE_MIDI 3
 148 #define RESOURCE_GAME 4
 149 #define RESOURCE_DDMA 7
 150
 151 #define SV_MIDI_DATA 0
 152 #define SV_MIDI_COMMAND 1
 153 #define SV_MIDI_STATUS 1
 154
 155 #define SV_DMA_ADDR0 0
 156 #define SV_DMA_ADDR1 1
 157 #define SV_DMA_ADDR2 2
 158 #define SV_DMA_ADDR3 3
 159 #define SV_DMA_COUNT0 4
 160 #define SV_DMA_COUNT1 5
 161 #define SV_DMA_COUNT2 6
 162 #define SV_DMA_MODE 0xb
 163 #define SV_DMA_RESET 0xd
 164 #define SV_DMA_MASK 0xf
 165
 166 /*
 167  * DONT reset the DMA controllers unless you understand
 168  * the reset semantics. Assuming reset semantics as in
 169  * the 8237 does not work.
 170  */
 171
 172 #define DMA_MODE_AUTOINIT 0x10
 173 #define DMA_MODE_READ 0x44/* I/O to memory, no autoinit, increment, single mode */
 174 #define DMA_MODE_WRITE 0x48/* memory to I/O, no autoinit, increment, single mode */
 175
 176 #define SV_CODEC_CONTROL 0
 177 #define SV_CODEC_INTMASK 1
 178 #define SV_CODEC_STATUS 2
 179 #define SV_CODEC_IADDR 4
 180 #define SV_CODEC_IDATA 5
 181
 182 #define SV_CCTRL_RESET 0x80
 183 #define SV_CCTRL_INTADRIVE 0x20
 184 #define SV_CCTRL_WAVETABLE 0x08
 185 #define SV_CCTRL_REVERB 0x04
 186 #define SV_CCTRL_ENHANCED 0x01
 187
 188 #define SV_CINTMASK_DMAA 0x01
 189 #define SV_CINTMASK_DMAC 0x04
 190 #define SV_CINTMASK_SPECIAL 0x08
 191 #define SV_CINTMASK_UPDOWN 0x40
 192 #define SV_CINTMASK_MIDI 0x80
 193
 194 #define SV_CSTAT_DMAA 0x01
 195 #define SV_CSTAT_DMAC 0x04
 196 #define SV_CSTAT_SPECIAL 0x08
 197 #define SV_CSTAT_UPDOWN 0x40
 198 #define SV_CSTAT_MIDI 0x80
 199
 200 #define SV_CIADDR_TRD 0x80
 201 #define SV_CIADDR_MCE 0x40
 202
 203 /* codec indirect registers */
 204 #define SV_CIMIX_ADCINL 0x00
 205 #define SV_CIMIX_ADCINR 0x01
 206 #define SV_CIMIX_AUX1INL 0x02
 207 #define SV_CIMIX_AUX1INR 0x03
 208 #define SV_CIMIX_CDINL 0x04
 209 #define SV_CIMIX_CDINR 0x05
 210 #define SV_CIMIX_LINEINL 0x06
 211 #define SV_CIMIX_LINEINR 0x07
 212 #define SV_CIMIX_MICIN 0x08
 213 #define SV_CIMIX_SYNTHINL 0x0A
 214 #define SV_CIMIX_SYNTHINR 0x0B
 215 #define SV_CIMIX_AUX2INL 0x0C
 216 #define SV_CIMIX_AUX2INR 0x0D
 217 #define SV_CIMIX_ANALOGINL 0x0E
 218 #define SV_CIMIX_ANALOGINR 0x0F
 219 #define SV_CIMIX_PCMINL 0x10
 220 #define SV_CIMIX_PCMINR 0x11
 221
 222 #define SV_CIGAMECONTROL 0x09
 223 #define SV_CIDATAFMT 0x12
 224 #define SV_CIENABLE 0x13
 225 #define SV_CIUPDOWN 0x14
 226 #define SV_CIREVISION 0x15
 227 #define SV_CIADCOUTPUT 0x16
 228 #define SV_CIDMAABASECOUNT1 0x18
 229 #define SV_CIDMAABASECOUNT0 0x19
 230 #define SV_CIDMACBASECOUNT1 0x1c
 231 #define SV_CIDMACBASECOUNT0 0x1d
 232 #define SV_CIPCMSR0 0x1e
 233 #define SV_CIPCMSR1 0x1f
 234 #define SV_CISYNTHSR0 0x20
 235 #define SV_CISYNTHSR1 0x21
 236 #define SV_CIADCCLKSOURCE 0x22
 237 #define SV_CIADCALTSR 0x23
 238 #define SV_CIADCPLLM 0x24
 239 #define SV_CIADCPLLN 0x25
 240 #define SV_CISYNTHPLLM 0x26
 241 #define SV_CISYNTHPLLN 0x27
 242 #define SV_CIUARTCONTROL 0x2a
 243 #define SV_CIDRIVECONTROL 0x2b
 244 #define SV_CISRSSPACE 0x2c
 245 #define SV_CISRSCENTER 0x2d
 246 #define SV_CIWAVETABLESRC 0x2e
 247 #define SV_CIANALOGPWRDOWN 0x30
 248 #define SV_CIDIGITALPWRDOWN 0x31
 249
 250
 251 #define SV_CIMIX_ADCSRC_CD 0x20
 252 #define SV_CIMIX_ADCSRC_DAC 0x40
 253 #define SV_CIMIX_ADCSRC_AUX2 0x60
 254 #define SV_CIMIX_ADCSRC_LINE 0x80
 255 #define SV_CIMIX_ADCSRC_AUX1 0xa0
 256 #define SV_CIMIX_ADCSRC_MIC 0xc0
 257 #define SV_CIMIX_ADCSRC_MIXOUT 0xe0
 258 #define SV_CIMIX_ADCSRC_MASK 0xe0
 259
 260 #define SV_CFMT_STEREO 0x01
 261 #define SV_CFMT_16BIT 0x02
 262 #define SV_CFMT_MASK 0x03
 263 #define SV_CFMT_ASHIFT 0
 264 #define SV_CFMT_CSHIFT 4
 265
 266 static const unsigned sample_size[] = {1,2,2,4};
 267 static const unsigned sample_shift[] = {0,1,1,2};
 268
 269 #define SV_CENABLE_PPE 0x4
 270 #define SV_CENABLE_RE 0x2
 271 #define SV_CENABLE_PE 0x1
 272
 273
 274 /* MIDI buffer sizes */
 275
 276 #define MIDIINBUF 256
 277 #define MIDIOUTBUF 256
 278
 279 #define FMODE_MIDI_SHIFT 2
 280 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
 281 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
 282
 283 #define FMODE_DMFM 0x10
 284
 285 /* --------------------------------------------------------------------- */
 286
 287 struct sv_state {
 288 /* magic */
 289 unsigned int magic;
 290
 291 /* list of sonicvibes devices */
 292 struct list_head devs;
 293
 294 /* the corresponding pci_dev structure */
 295 struct pci_dev *dev;
 296
 297 /* soundcore stuff */
 298 int dev_audio;
 299 int dev_mixer;
 300 int dev_midi;
 301 int dev_dmfm;
 302
 303 /* hardware resources */
 304 unsigned long iosb, ioenh, iosynth, iomidi, iogame;/* long for SPARC */
 305 unsigned int iodmaa, iodmac, irq;
 306
 307 /* mixer stuff */
 308 struct{
 309 unsigned int modcnt;
 310 #ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
 311 unsigned short vol[13];
 312 #endif/* OSS_DOCUMENTED_MIXER_SEMANTICS */
 313 } mix;
 314
 315 /* wave stuff */
 316 unsigned int rateadc, ratedac;
 317 unsigned char fmt, enable;
 318
 319  spinlock_t lock;
 320 struct semaphore open_sem;
 321  mode_t open_mode;
 322  wait_queue_head_t open_wait;
 323
 324 struct dmabuf {
 325 void*rawbuf;
 326  dma_addr_t dmaaddr;
 327 unsigned buforder;
 328 unsigned numfrag;
 329 unsigned fragshift;
 330 unsigned hwptr, swptr;
 331 unsigned total_bytes;
 332 int count;
 333 unsigned error;/* over/underrun */
 334  wait_queue_head_t wait;
 335 /* redundant, but makes calculations easier */
 336 unsigned fragsize;
 337 unsigned dmasize;
 338 unsigned fragsamples;
 339 /* OSS stuff */
 340 unsigned mapped:1;
 341 unsigned ready:1;
 342 unsigned endcleared:1;
 343 unsigned ossfragshift;
 344 int ossmaxfrags;
 345 unsigned subdivision;
 346 } dma_dac, dma_adc;
 347
 348 /* midi stuff */
 349 struct{
 350 unsigned ird, iwr, icnt;
 351 unsigned ord, owr, ocnt;
 352  wait_queue_head_t iwait;
 353  wait_queue_head_t owait;
 354 struct timer_list timer;
 355 unsigned char ibuf[MIDIINBUF];
 356 unsigned char obuf[MIDIOUTBUF];
 357 } midi;
 358 };
 359
 360 /* --------------------------------------------------------------------- */
 361
 362 staticLIST_HEAD(devs);
 363 static unsigned long wavetable_mem =0;
 364
 365 /* --------------------------------------------------------------------- */
 366
 367 extern __inline__ unsignedld2(unsigned int x)
 368 {
 369 unsigned r =0;
 370
 371 if(x >=0x10000) {
 372  x >>=16;
 373  r +=16;
 374 }
 375 if(x >=0x100) {
 376  x >>=8;
 377  r +=8;
 378 }
 379 if(x >=0x10) {
 380  x >>=4;
 381  r +=4;
 382 }
 383 if(x >=4) {
 384  x >>=2;
 385  r +=2;
 386 }
 387 if(x >=2)
 388  r++;
 389 return r;
 390 }
 391
 392 /*
 393  * hweightN: returns the hamming weight (i.e. the number
 394  * of bits set) of a N-bit word
 395  */
 396
 397 #ifdef hweight32
 398 #undef hweight32
 399 #endif
 400
 401 extern __inline__ unsigned inthweight32(unsigned int w)
 402 {
 403 unsigned int res = (w &0x55555555) + ((w >>1) &0x55555555);
 404  res = (res &0x33333333) + ((res >>2) &0x33333333);
 405  res = (res &0x0F0F0F0F) + ((res >>4) &0x0F0F0F0F);
 406  res = (res &0x00FF00FF) + ((res >>8) &0x00FF00FF);
 407 return(res &0x0000FFFF) + ((res >>16) &0x0000FFFF);
 408 }
 409
 410 /* --------------------------------------------------------------------- */
 411
 412 /*
 413  * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
 414  */
 415
 416 #undef DMABYTEIO
 417
 418 static voidset_dmaa(struct sv_state *s,unsigned int addr,unsigned int count)
 419 {
 420 #ifdef DMABYTEIO
 421 unsigned io = s->iodmaa, u;
 422
 423  count--;
 424 for(u =4; u >0; u--, addr >>=8, io++)
 425 outb(addr &0xff, io);
 426 for(u =3; u >0; u--, count >>=8, io++)
 427 outb(count &0xff, io);
 428 #else/* DMABYTEIO */
 429  count--;
 430 outl(addr, s->iodmaa + SV_DMA_ADDR0);
 431 outl(count, s->iodmaa + SV_DMA_COUNT0);
 432 #endif/* DMABYTEIO */
 433 outb(0x18, s->iodmaa + SV_DMA_MODE);
 434 }
 435
 436 static voidset_dmac(struct sv_state *s,unsigned int addr,unsigned int count)
 437 {
 438 #ifdef DMABYTEIO
 439 unsigned io = s->iodmac, u;
 440
 441  count >>=1;
 442  count--;
 443 for(u =4; u >0; u--, addr >>=8, io++)
 444 outb(addr &0xff, io);
 445 for(u =3; u >0; u--, count >>=8, io++)
 446 outb(count &0xff, io);
 447 #else/* DMABYTEIO */
 448  count >>=1;
 449  count--;
 450 outl(addr, s->iodmac + SV_DMA_ADDR0);
 451 outl(count, s->iodmac + SV_DMA_COUNT0);
 452 #endif/* DMABYTEIO */
 453 outb(0x14, s->iodmac + SV_DMA_MODE);
 454 }
 455
 456 extern __inline__ unsignedget_dmaa(struct sv_state *s)
 457 {
 458 #ifdef DMABYTEIO
 459 unsigned io = s->iodmaa+6, v =0, u;
 460
 461 for(u =3; u >0; u--, io--) {
 462  v <<=8;
 463  v |=inb(io);
 464 }
 465 return v +1;
 466 #else/* DMABYTEIO */
 467 return(inl(s->iodmaa + SV_DMA_COUNT0) &0xffffff) +1;
 468 #endif/* DMABYTEIO */
 469 }
 470
 471 extern __inline__ unsignedget_dmac(struct sv_state *s)
 472 {
 473 #ifdef DMABYTEIO
 474 unsigned io = s->iodmac+6, v =0, u;
 475
 476 for(u =3; u >0; u--, io--) {
 477  v <<=8;
 478  v |=inb(io);
 479 }
 480 return(v +1) <<1;
 481 #else/* DMABYTEIO */
 482 return((inl(s->iodmac + SV_DMA_COUNT0) &0xffffff) +1) <<1;
 483 #endif/* DMABYTEIO */
 484 }
 485
 486 static voidwrindir(struct sv_state *s,unsigned char idx,unsigned char data)
 487 {
 488 outb(idx &0x3f, s->ioenh + SV_CODEC_IADDR);
 489 udelay(10);
 490 outb(data, s->ioenh + SV_CODEC_IDATA);
 491 udelay(10);
 492 }
 493
 494 static unsigned charrdindir(struct sv_state *s,unsigned char idx)
 495 {
 496 unsigned char v;
 497
 498 outb(idx &0x3f, s->ioenh + SV_CODEC_IADDR);
 499 udelay(10);
 500  v =inb(s->ioenh + SV_CODEC_IDATA);
 501 udelay(10);
 502 return v;
 503 }
 504
 505 static voidset_fmt(struct sv_state *s,unsigned char mask,unsigned char data)
 506 {
 507 unsigned long flags;
 508
 509 spin_lock_irqsave(&s->lock, flags);
 510 outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
 511 if(mask) {
 512  s->fmt =inb(s->ioenh + SV_CODEC_IDATA);
 513 udelay(10);
 514 }
 515  s->fmt = (s->fmt & mask) | data;
 516 outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
 517 udelay(10);
 518 outb(0, s->ioenh + SV_CODEC_IADDR);
 519 spin_unlock_irqrestore(&s->lock, flags);
 520 udelay(10);
 521 }
 522
 523 static voidfrobindir(struct sv_state *s,unsigned char idx,unsigned char mask,unsigned char data)
 524 {
 525 outb(idx &0x3f, s->ioenh + SV_CODEC_IADDR);
 526 udelay(10);
 527 outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
 528 udelay(10);
 529 }
 530
 531 #define REFFREQUENCY 24576000
 532 #define ADCMULT 512
 533 #define FULLRATE 48000
 534
 535 static unsignedsetpll(struct sv_state *s,unsigned char reg,unsigned rate)
 536 {
 537 unsigned long flags;
 538 unsigned char r, m=0, n=0;
 539 unsigned xm, xn, xr, xd, metric = ~0U;
 540 /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
 541
 542 if(rate <625000/ADCMULT)
 543  rate =625000/ADCMULT;
 544 if(rate >150000000/ADCMULT)
 545  rate =150000000/ADCMULT;
 546 /* slight violation of specs, needed for continuous sampling rates */
 547 for(r =0; rate <75000000/ADCMULT; r +=0x20, rate <<=1);
 548 for(xn =3; xn <35; xn++)
 549 for(xm =3; xm <130; xm++) {
 550  xr = REFFREQUENCY/ADCMULT * xm / xn;
 551  xd =abs((signed)(xr - rate));
 552 if(xd < metric) {
 553  metric = xd;
 554  m = xm -2;
 555  n = xn -2;
 556 }
 557 }
 558  reg &=0x3f;
 559 spin_lock_irqsave(&s->lock, flags);
 560 outb(reg, s->ioenh + SV_CODEC_IADDR);
 561 udelay(10);
 562 outb(m, s->ioenh + SV_CODEC_IDATA);
 563 udelay(10);
 564 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
 565 udelay(10);
 566 outb(r | n, s->ioenh + SV_CODEC_IDATA);
 567 spin_unlock_irqrestore(&s->lock, flags);
 568 udelay(10);
 569 return(REFFREQUENCY/ADCMULT * (m +2) / (n +2)) >> ((r >>5) &7);
 570 }
 571
 572 #if 0
 573
 574 static unsignedgetpll(struct sv_state *s,unsigned char reg)
 575 {
 576 unsigned long flags;
 577 unsigned char m, n;
 578
 579  reg &=0x3f;
 580 spin_lock_irqsave(&s->lock, flags);
 581 outb(reg, s->ioenh + SV_CODEC_IADDR);
 582 udelay(10);
 583  m =inb(s->ioenh + SV_CODEC_IDATA);
 584 udelay(10);
 585 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
 586 udelay(10);
 587  n =inb(s->ioenh + SV_CODEC_IDATA);
 588 spin_unlock_irqrestore(&s->lock, flags);
 589 udelay(10);
 590 return(REFFREQUENCY/ADCMULT * (m +2) / ((n &0x1f) +2)) >> ((n >>5) &7);
 591 }
 592
 593 #endif
 594
 595 static voidset_dac_rate(struct sv_state *s,unsigned rate)
 596 {
 597 unsigned div;
 598 unsigned long flags;
 599
 600 if(rate >48000)
 601  rate =48000;
 602 if(rate <4000)
 603  rate =4000;
 604  div = (rate *65536+ FULLRATE/2) / FULLRATE;
 605 if(div >65535)
 606  div =65535;
 607 spin_lock_irqsave(&s->lock, flags);
 608 wrindir(s, SV_CIPCMSR1, div >>8);
 609 wrindir(s, SV_CIPCMSR0, div);
 610 spin_unlock_irqrestore(&s->lock, flags);
 611  s->ratedac = (div * FULLRATE +32768) /65536;
 612 }
 613
 614 static voidset_adc_rate(struct sv_state *s,unsigned rate)
 615 {
 616 unsigned long flags;
 617 unsigned rate1, rate2, div;
 618
 619 if(rate >48000)
 620  rate =48000;
 621 if(rate <4000)
 622  rate =4000;
 623  rate1 =setpll(s, SV_CIADCPLLM, rate);
 624  div = (48000+ rate/2) / rate;
 625 if(div >8)
 626  div =8;
 627  rate2 = (48000+ div/2) / div;
 628 spin_lock_irqsave(&s->lock, flags);
 629 wrindir(s, SV_CIADCALTSR, (div-1) <<4);
 630 if(abs((signed)(rate-rate2)) <=abs((signed)(rate-rate1))) {
 631 wrindir(s, SV_CIADCCLKSOURCE,0x10);
 632  s->rateadc = rate2;
 633 }else{
 634 wrindir(s, SV_CIADCCLKSOURCE,0x00);
 635  s->rateadc = rate1;
 636 }
 637 spin_unlock_irqrestore(&s->lock, flags);
 638 }
 639
 640 /* --------------------------------------------------------------------- */
 641
 642 extern inlinevoidstop_adc(struct sv_state *s)
 643 {
 644 unsigned long flags;
 645
 646 spin_lock_irqsave(&s->lock, flags);
 647  s->enable &= ~SV_CENABLE_RE;
 648 wrindir(s, SV_CIENABLE, s->enable);
 649 spin_unlock_irqrestore(&s->lock, flags);
 650 }
 651
 652 extern inlinevoidstop_dac(struct sv_state *s)
 653 {
 654 unsigned long flags;
 655
 656 spin_lock_irqsave(&s->lock, flags);
 657  s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
 658 wrindir(s, SV_CIENABLE, s->enable);
 659 spin_unlock_irqrestore(&s->lock, flags);
 660 }
 661
 662 static voidstart_dac(struct sv_state *s)
 663 {
 664 unsigned long flags;
 665
 666 spin_lock_irqsave(&s->lock, flags);
 667 if((s->dma_dac.mapped || s->dma_dac.count >0) && s->dma_dac.ready) {
 668  s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
 669 wrindir(s, SV_CIENABLE, s->enable);
 670 }
 671 spin_unlock_irqrestore(&s->lock, flags);
 672 }
 673
 674 static voidstart_adc(struct sv_state *s)
 675 {
 676 unsigned long flags;
 677
 678 spin_lock_irqsave(&s->lock, flags);
 679 if((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize -2*s->dma_adc.fragsize))
 680 && s->dma_adc.ready) {
 681  s->enable |= SV_CENABLE_RE;
 682 wrindir(s, SV_CIENABLE, s->enable);
 683 }
 684 spin_unlock_irqrestore(&s->lock, flags);
 685 }
 686
 687 /* --------------------------------------------------------------------- */
 688
 689 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
 690 #define DMABUF_MINORDER 1
 691
 692 static voiddealloc_dmabuf(struct sv_state *s,struct dmabuf *db)
 693 {
 694 struct page *page, *pend;
 695
 696 if(db->rawbuf) {
 697 /* undo marking the pages as reserved */
 698  pend =virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -1);
 699 for(page =virt_to_page(db->rawbuf); page <= pend; page++)
 700 mem_map_unreserve(page);
 701 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
 702 }
 703  db->rawbuf = NULL;
 704  db->mapped = db->ready =0;
 705 }
 706
 707
 708 /* DMAA is used for playback, DMAC is used for recording */
 709
 710 static intprog_dmabuf(struct sv_state *s,unsigned rec)
 711 {
 712 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
 713 unsigned rate = rec ? s->rateadc : s->ratedac;
 714 int order;
 715 unsigned bytepersec;
 716 unsigned bufs;
 717 struct page *page, *pend;
 718 unsigned char fmt;
 719 unsigned long flags;
 720
 721 spin_lock_irqsave(&s->lock, flags);
 722  fmt = s->fmt;
 723 if(rec) {
 724  s->enable &= ~SV_CENABLE_RE;
 725  fmt >>= SV_CFMT_CSHIFT;
 726 }else{
 727  s->enable &= ~SV_CENABLE_PE;
 728  fmt >>= SV_CFMT_ASHIFT;
 729 }
 730 wrindir(s, SV_CIENABLE, s->enable);
 731 spin_unlock_irqrestore(&s->lock, flags);
 732  fmt &= SV_CFMT_MASK;
 733  db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared =0;
 734 if(!db->rawbuf) {
 735  db->ready = db->mapped =0;
 736 for(order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
 737 if((db->rawbuf =pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
 738 break;
 739 if(!db->rawbuf)
 740 return-ENOMEM;
 741  db->buforder = order;
 742 if((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) -1)) & ~0xffff)
 743 printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
 744 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
 745 if((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) -1) & ~0xffffff)
 746 printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
 747 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
 748 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
 749  pend =virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -1);
 750 for(page =virt_to_page(db->rawbuf); page <= pend; page++)
 751 mem_map_reserve(page);
 752 }
 753  bytepersec = rate << sample_shift[fmt];
 754  bufs = PAGE_SIZE << db->buforder;
 755 if(db->ossfragshift) {
 756 if((1000<< db->ossfragshift) < bytepersec)
 757  db->fragshift =ld2(bytepersec/1000);
 758 else
 759  db->fragshift = db->ossfragshift;
 760 }else{
 761  db->fragshift =ld2(bytepersec/100/(db->subdivision ? db->subdivision :1));
 762 if(db->fragshift <3)
 763  db->fragshift =3;
 764 }
 765  db->numfrag = bufs >> db->fragshift;
 766 while(db->numfrag <4&& db->fragshift >3) {
 767  db->fragshift--;
 768  db->numfrag = bufs >> db->fragshift;
 769 }
 770  db->fragsize =1<< db->fragshift;
 771 if(db->ossmaxfrags >=4&& db->ossmaxfrags < db->numfrag)
 772  db->numfrag = db->ossmaxfrags;
 773  db->fragsamples = db->fragsize >> sample_shift[fmt];
 774  db->dmasize = db->numfrag << db->fragshift;
 775 memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ?0:0x80, db->dmasize);
 776 spin_lock_irqsave(&s->lock, flags);
 777 if(rec) {
 778 set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
 779 /* program enhanced mode registers */
 780 wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >>8);
 781 wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
 782 }else{
 783 set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
 784 /* program enhanced mode registers */
 785 wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >>8);
 786 wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
 787 }
 788 spin_unlock_irqrestore(&s->lock, flags);
 789  db->ready =1;
 790 return0;
 791 }
 792
 793 extern __inline__ voidclear_advance(struct sv_state *s)
 794 {
 795 unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ?0:0x80;
 796 unsigned char*buf = s->dma_dac.rawbuf;
 797 unsigned bsize = s->dma_dac.dmasize;
 798 unsigned bptr = s->dma_dac.swptr;
 799 unsigned len = s->dma_dac.fragsize;
 800
 801 if(bptr + len > bsize) {
 802 unsigned x = bsize - bptr;
 803 memset(buf + bptr, c, x);
 804  bptr =0;
 805  len -= x;
 806 }
 807 memset(buf + bptr, c, len);
 808 }
 809
 810 /* call with spinlock held! */
 811 static voidsv_update_ptr(struct sv_state *s)
 812 {
 813 unsigned hwptr;
 814 int diff;
 815
 816 /* update ADC pointer */
 817 if(s->dma_adc.ready) {
 818  hwptr = (s->dma_adc.dmasize -get_dmac(s)) % s->dma_adc.dmasize;
 819  diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
 820  s->dma_adc.hwptr = hwptr;
 821  s->dma_adc.total_bytes += diff;
 822  s->dma_adc.count += diff;
 823 if(s->dma_adc.count >= (signed)s->dma_adc.fragsize)
 824 wake_up(&s->dma_adc.wait);
 825 if(!s->dma_adc.mapped) {
 826 if(s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3* s->dma_adc.fragsize) >>1))) {
 827  s->enable &= ~SV_CENABLE_RE;
 828 wrindir(s, SV_CIENABLE, s->enable);
 829  s->dma_adc.error++;
 830 }
 831 }
 832 }
 833 /* update DAC pointer */
 834 if(s->dma_dac.ready) {
 835  hwptr = (s->dma_dac.dmasize -get_dmaa(s)) % s->dma_dac.dmasize;
 836  diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
 837  s->dma_dac.hwptr = hwptr;
 838  s->dma_dac.total_bytes += diff;
 839 if(s->dma_dac.mapped) {
 840  s->dma_dac.count += diff;
 841 if(s->dma_dac.count >= (signed)s->dma_dac.fragsize)
 842 wake_up(&s->dma_dac.wait);
 843 }else{
 844  s->dma_dac.count -= diff;
 845 if(s->dma_dac.count <=0) {
 846  s->enable &= ~SV_CENABLE_PE;
 847 wrindir(s, SV_CIENABLE, s->enable);
 848  s->dma_dac.error++;
 849 }else if(s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
 850 clear_advance(s);
 851  s->dma_dac.endcleared =1;
 852 }
 853 if(s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
 854 wake_up(&s->dma_dac.wait);
 855 }
 856 }
 857 }
 858
 859 /* hold spinlock for the following! */
 860 static voidsv_handle_midi(struct sv_state *s)
 861 {
 862 unsigned char ch;
 863 int wake;
 864
 865  wake =0;
 866 while(!(inb(s->iomidi+1) &0x80)) {
 867  ch =inb(s->iomidi);
 868 if(s->midi.icnt < MIDIINBUF) {
 869  s->midi.ibuf[s->midi.iwr] = ch;
 870  s->midi.iwr = (s->midi.iwr +1) % MIDIINBUF;
 871  s->midi.icnt++;
 872 }
 873  wake =1;
 874 }
 875 if(wake)
 876 wake_up(&s->midi.iwait);
 877  wake =0;
 878 while(!(inb(s->iomidi+1) &0x40) && s->midi.ocnt >0) {
 879 outb(s->midi.obuf[s->midi.ord], s->iomidi);
 880  s->midi.ord = (s->midi.ord +1) % MIDIOUTBUF;
 881  s->midi.ocnt--;
 882 if(s->midi.ocnt < MIDIOUTBUF-16)
 883  wake =1;
 884 }
 885 if(wake)
 886 wake_up(&s->midi.owait);
 887 }
 888
 889 static voidsv_interrupt(int irq,void*dev_id,struct pt_regs *regs)
 890 {
 891 struct sv_state *s = (struct sv_state *)dev_id;
 892 unsigned int intsrc;
 893
 894 /* fastpath out, to ease interrupt sharing */
 895  intsrc =inb(s->ioenh + SV_CODEC_STATUS);
 896 if(!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
 897 return;
 898 spin_lock(&s->lock);
 899 sv_update_ptr(s);
 900 sv_handle_midi(s);
 901 spin_unlock(&s->lock);
 902 }
 903
 904 static voidsv_midi_timer(unsigned long data)
 905 {
 906 struct sv_state *s = (struct sv_state *)data;
 907 unsigned long flags;
 908
 909 spin_lock_irqsave(&s->lock, flags);
 910 sv_handle_midi(s);
 911 spin_unlock_irqrestore(&s->lock, flags);
 912  s->midi.timer.expires = jiffies+1;
 913 add_timer(&s->midi.timer);
 914 }
 915
 916 /* --------------------------------------------------------------------- */
 917
 918 static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
 919
 920 #define VALIDATE_STATE(s) \
 921 ({ \
 922  if (!(s) || (s)->magic != SV_MAGIC) { \
 923  printk(invalid_magic); \
 924  return -ENXIO; \
 925  } \
 926 })
 927
 928 /* --------------------------------------------------------------------- */
 929
 930 #define MT_4 1
 931 #define MT_5MUTE 2
 932 #define MT_4MUTEMONO 3
 933 #define MT_6MUTE 4
 934
 935 static const struct{
 936 unsigned left:5;
 937 unsigned right:5;
 938 unsigned type:3;
 939 unsigned rec:3;
 940 } mixtable[SOUND_MIXER_NRDEVICES] = {
 941 [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4,0},
 942 [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE,5},
 943 [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE,1},
 944 [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE,4},
 945 [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO,6},
 946 [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE,2},
 947 [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE,3},
 948 [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE,7},
 949 [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE,0}
 950 };
 951
 952 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
 953
 954 static intreturn_mixval(struct sv_state *s,unsigned i,int*arg)
 955 {
 956 unsigned long flags;
 957 unsigned char l, r, rl, rr;
 958
 959 spin_lock_irqsave(&s->lock, flags);
 960  l =rdindir(s, mixtable[i].left);
 961  r =rdindir(s, mixtable[i].right);
 962 spin_unlock_irqrestore(&s->lock, flags);
 963 switch(mixtable[i].type) {
 964 case MT_4:
 965  r &=0xf;
 966  l &=0xf;
 967  rl =10+6* (l &15);
 968  rr =10+6* (r &15);
 969 break;
 970
 971 case MT_4MUTEMONO:
 972  rl =55-3* (l &15);
 973 if(r &0x10)
 974  rl +=45;
 975  rr = rl;
 976  r = l;
 977 break;
 978
 979 case MT_5MUTE:
 980 default:
 981  rl =100-3* (l &31);
 982  rr =100-3* (r &31);
 983 break;
 984
 985 case MT_6MUTE:
 986  rl =100-3* (l &63) /2;
 987  rr =100-3* (r &63) /2;
 988 break;
 989 }
 990 if(l &0x80)
 991  rl =0;
 992 if(r &0x80)
 993  rr =0;
 994 returnput_user((rr <<8) | rl, arg);
 995 }
 996
 997 #else/* OSS_DOCUMENTED_MIXER_SEMANTICS */
 998
 999 static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1000 {
1001 [SOUND_MIXER_RECLEV] =1,
1002 [SOUND_MIXER_LINE1] =2,
1003 [SOUND_MIXER_CD] =3,
1004 [SOUND_MIXER_LINE] =4,
1005 [SOUND_MIXER_MIC] =5,
1006 [SOUND_MIXER_SYNTH] =6,
1007 [SOUND_MIXER_LINE2] =7,
1008 [SOUND_MIXER_VOLUME] =8,
1009 [SOUND_MIXER_PCM] =9
1010 };
1011
1012 #endif/* OSS_DOCUMENTED_MIXER_SEMANTICS */
1013
1014 static unsignedmixer_recmask(struct sv_state *s)
1015 {
1016 unsigned long flags;
1017 int i, j;
1018
1019 spin_lock_irqsave(&s->lock, flags);
1020  j =rdindir(s, SV_CIMIX_ADCINL) >>5;
1021 spin_unlock_irqrestore(&s->lock, flags);
1022  j &=7;
1023 for(i =0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
1024 return1<< i;
1025 }
1026
1027 static intmixer_ioctl(struct sv_state *s,unsigned int cmd,unsigned long arg)
1028 {
1029 unsigned long flags;
1030 int i, val;
1031 unsigned char l, r, rl, rr;
1032
1033 VALIDATE_STATE(s);
1034 if(cmd == SOUND_MIXER_INFO) {
1035  mixer_info info;
1036 strncpy(info.id,"SonicVibes",sizeof(info.id));
1037 strncpy(info.name,"S3 SonicVibes",sizeof(info.name));
1038  info.modify_counter = s->mix.modcnt;
1039 if(copy_to_user((void*)arg, &info,sizeof(info)))
1040 return-EFAULT;
1041 return0;
1042 }
1043 if(cmd == SOUND_OLD_MIXER_INFO) {
1044  _old_mixer_info info;
1045 strncpy(info.id,"SonicVibes",sizeof(info.id));
1046 strncpy(info.name,"S3 SonicVibes",sizeof(info.name));
1047 if(copy_to_user((void*)arg, &info,sizeof(info)))
1048 return-EFAULT;
1049 return0;
1050 }
1051 if(cmd == OSS_GETVERSION)
1052 returnput_user(SOUND_VERSION, (int*)arg);
1053 if(cmd == SOUND_MIXER_PRIVATE1) {/* SRS settings */
1054 if(get_user(val, (int*)arg))
1055 return-EFAULT;
1056 spin_lock_irqsave(&s->lock, flags);
1057 if(val &1) {
1058 if(val &2) {
1059  l =4- ((val >>2) &7);
1060 if(l & ~3)
1061  l =4;
1062  r =4- ((val >>5) &7);
1063 if(r & ~3)
1064  r =4;
1065 wrindir(s, SV_CISRSSPACE, l);
1066 wrindir(s, SV_CISRSCENTER, r);
1067 }else
1068 wrindir(s, SV_CISRSSPACE,0x80);
1069 }
1070  l =rdindir(s, SV_CISRSSPACE);
1071  r =rdindir(s, SV_CISRSCENTER);
1072 spin_unlock_irqrestore(&s->lock, flags);
1073 if(l &0x80)
1074 returnput_user(0, (int*)arg);
1075 returnput_user(((4- (l &7)) <<2) | ((4- (r &7)) <<5) |2, (int*)arg);
1076 }
1077 if(_IOC_TYPE(cmd) !='M'||_SIOC_SIZE(cmd) !=sizeof(int))
1078 return-EINVAL;
1079 if(_SIOC_DIR(cmd) == _SIOC_READ) {
1080 switch(_IOC_NR(cmd)) {
1081 case SOUND_MIXER_RECSRC:/* Arg contains a bit for each recording source */
1082 returnput_user(mixer_recmask(s), (int*)arg);
1083
1084 case SOUND_MIXER_DEVMASK:/* Arg contains a bit for each supported device */
1085 for(val = i =0; i < SOUND_MIXER_NRDEVICES; i++)
1086 if(mixtable[i].type)
1087  val |=1<< i;
1088 returnput_user(val, (int*)arg);
1089
1090 case SOUND_MIXER_RECMASK:/* Arg contains a bit for each supported recording source */
1091 for(val = i =0; i < SOUND_MIXER_NRDEVICES; i++)
1092 if(mixtable[i].rec)
1093  val |=1<< i;
1094 returnput_user(val, (int*)arg);
1095
1096 case SOUND_MIXER_STEREODEVS:/* Mixer channels supporting stereo */
1097 for(val = i =0; i < SOUND_MIXER_NRDEVICES; i++)
1098 if(mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1099  val |=1<< i;
1100 returnput_user(val, (int*)arg);
1101
1102 case SOUND_MIXER_CAPS:
1103 returnput_user(SOUND_CAP_EXCL_INPUT, (int*)arg);
1104
1105 default:
1106  i =_IOC_NR(cmd);
1107 if(i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1108 return-EINVAL;
1109 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1110 returnreturn_mixval(s, i, (int*)arg);
1111 #else/* OSS_DOCUMENTED_MIXER_SEMANTICS */
1112 if(!volidx[i])
1113 return-EINVAL;
1114 returnput_user(s->mix.vol[volidx[i]-1], (int*)arg);
1115 #endif/* OSS_DOCUMENTED_MIXER_SEMANTICS */
1116 }
1117 }
1118 if(_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1119 return-EINVAL;
1120  s->mix.modcnt++;
1121 switch(_IOC_NR(cmd)) {
1122 case SOUND_MIXER_RECSRC:/* Arg contains a bit for each recording source */
1123 if(get_user(val, (int*)arg))
1124 return-EFAULT;
1125  i =hweight32(val);
1126 if(i ==0)
1127 return0;/*val = mixer_recmask(s);*/
1128 else if(i >1)
1129  val &= ~mixer_recmask(s);
1130 for(i =0; i < SOUND_MIXER_NRDEVICES; i++) {
1131 if(!(val & (1<< i)))
1132 continue;
1133 if(mixtable[i].rec)
1134 break;
1135 }
1136 if(!mixtable[i].rec)
1137 return0;
1138 spin_lock_irqsave(&s->lock, flags);
1139 frobindir(s, SV_CIMIX_ADCINL,0x1f, mixtable[i].rec <<5);
1140 frobindir(s, SV_CIMIX_ADCINR,0x1f, mixtable[i].rec <<5);
1141 spin_unlock_irqrestore(&s->lock, flags);
1142 return0;
1143
1144 default:
1145  i =_IOC_NR(cmd);
1146 if(i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1147 return-EINVAL;
1148 if(get_user(val, (int*)arg))
1149 return-EFAULT;
1150  l = val &0xff;
1151  r = (val >>8) &0xff;
1152 if(mixtable[i].type == MT_4MUTEMONO)
1153  l = (r + l) /2;
1154 if(l >100)
1155  l =100;
1156 if(r >100)
1157  r =100;
1158 spin_lock_irqsave(&s->lock, flags);
1159 switch(mixtable[i].type) {
1160 case MT_4:
1161 if(l >=10)
1162  l -=10;
1163 if(r >=10)
1164  r -=10;
1165 frobindir(s, mixtable[i].left,0xf0, l /6);
1166 frobindir(s, mixtable[i].right,0xf0, l /6);
1167 break;
1168
1169 case MT_4MUTEMONO:
1170  rr =0;
1171 if(l <10)
1172  rl =0x80;
1173 else{
1174 if(l >=55) {
1175  rr =0x10;
1176  l -=45;
1177 }
1178  rl = (55- l) /3;
1179 }
1180 wrindir(s, mixtable[i].left, rl);
1181 frobindir(s, mixtable[i].right, ~0x10, rr);
1182 break;
1183
1184 case MT_5MUTE:
1185 if(l <7)
1186  rl =0x80;
1187 else
1188  rl = (100- l) /3;
1189 if(r <7)
1190  rr =0x80;
1191 else
1192  rr = (100- r) /3;
1193 wrindir(s, mixtable[i].left, rl);
1194 wrindir(s, mixtable[i].right, rr);
1195 break;
1196
1197 case MT_6MUTE:
1198 if(l <6)
1199  rl =0x80;
1200 else
1201  rl = (100- l) *2/3;
1202 if(r <6)
1203  rr =0x80;
1204 else
1205  rr = (100- r) *2/3;
1206 wrindir(s, mixtable[i].left, rl);
1207 wrindir(s, mixtable[i].right, rr);
1208 break;
1209 }
1210 spin_unlock_irqrestore(&s->lock, flags);
1211 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1212 returnreturn_mixval(s, i, (int*)arg);
1213 #else/* OSS_DOCUMENTED_MIXER_SEMANTICS */
1214 if(!volidx[i])
1215 return-EINVAL;
1216  s->mix.vol[volidx[i]-1] = val;
1217 returnput_user(s->mix.vol[volidx[i]-1], (int*)arg);
1218 #endif/* OSS_DOCUMENTED_MIXER_SEMANTICS */
1219 }
1220 }
1221
1222 /* --------------------------------------------------------------------- */
1223
1224 static loff_t sv_llseek(struct file *file, loff_t offset,int origin)
1225 {
1226 return-ESPIPE;
1227 }
1228
1229 /* --------------------------------------------------------------------- */
1230
1231 static intsv_open_mixdev(struct inode *inode,struct file *file)
1232 {
1233 int minor =MINOR(inode->i_rdev);
1234 struct list_head *list;
1235 struct sv_state *s;
1236
1237 for(list = devs.next; ; list = list->next) {
1238 if(list == &devs)
1239 return-ENODEV;
1240  s =list_entry(list,struct sv_state, devs);
1241 if(s->dev_mixer == minor)
1242 break;
1243 }
1244 VALIDATE_STATE(s);
1245  file->private_data = s;
1246 return0;
1247 }
1248
1249 static intsv_release_mixdev(struct inode *inode,struct file *file)
1250 {
1251 struct sv_state *s = (struct sv_state *)file->private_data;
1252
1253 VALIDATE_STATE(s);
1254 return0;
1255 }
1256
1257 static intsv_ioctl_mixdev(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
1258 {
1259 returnmixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
1260 }
1261
1262 static/*const*/struct file_operations sv_mixer_fops = {
1263  owner: THIS_MODULE,
1264  llseek: sv_llseek,
1265  ioctl: sv_ioctl_mixdev,
1266  open: sv_open_mixdev,
1267  release: sv_release_mixdev,
1268 };
1269
1270 /* --------------------------------------------------------------------- */
1271
1272 static intdrain_dac(struct sv_state *s,int nonblock)
1273 {
1274 DECLARE_WAITQUEUE(wait, current);
1275 unsigned long flags;
1276 int count, tmo;
1277
1278 if(s->dma_dac.mapped || !s->dma_dac.ready)
1279 return0;
1280 add_wait_queue(&s->dma_dac.wait, &wait);
1281 for(;;) {
1282 __set_current_state(TASK_INTERRUPTIBLE);
1283 spin_lock_irqsave(&s->lock, flags);
1284  count = s->dma_dac.count;
1285 spin_unlock_irqrestore(&s->lock, flags);
1286 if(count <=0)
1287 break;
1288 if(signal_pending(current))
1289 break;
1290 if(nonblock) {
1291 remove_wait_queue(&s->dma_dac.wait, &wait);
1292 set_current_state(TASK_RUNNING);
1293 return-EBUSY;
1294 }
1295  tmo =3* HZ * (count + s->dma_dac.fragsize) /2/ s->ratedac;
1296  tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
1297 if(!schedule_timeout(tmo +1))
1298 printk(KERN_DEBUG "sv: dma timed out??\n");
1299 }
1300 remove_wait_queue(&s->dma_dac.wait, &wait);
1301 set_current_state(TASK_RUNNING);
1302 if(signal_pending(current))
1303 return-ERESTARTSYS;
1304 return0;
1305 }
1306
1307 /* --------------------------------------------------------------------- */
1308
1309 static ssize_t sv_read(struct file *file,char*buffer,size_t count, loff_t *ppos)
1310 {
1311 struct sv_state *s = (struct sv_state *)file->private_data;
1312 DECLARE_WAITQUEUE(wait, current);
1313  ssize_t ret;
1314 unsigned long flags;
1315 unsigned swptr;
1316 int cnt;
1317
1318 VALIDATE_STATE(s);
1319 if(ppos != &file->f_pos)
1320 return-ESPIPE;
1321 if(s->dma_adc.mapped)
1322 return-ENXIO;
1323 if(!s->dma_adc.ready && (ret =prog_dmabuf(s,1)))
1324 return ret;
1325 if(!access_ok(VERIFY_WRITE, buffer, count))
1326 return-EFAULT;
1327  ret =0;
1328 #if 0
1329 spin_lock_irqsave(&s->lock, flags);
1330 sv_update_ptr(s);
1331 spin_unlock_irqrestore(&s->lock, flags);
1332 #endif
1333 add_wait_queue(&s->dma_adc.wait, &wait);
1334 while(count >0) {
1335 spin_lock_irqsave(&s->lock, flags);
1336  swptr = s->dma_adc.swptr;
1337  cnt = s->dma_adc.dmasize-swptr;
1338 if(s->dma_adc.count < cnt)
1339  cnt = s->dma_adc.count;
1340 if(cnt <=0)
1341 __set_current_state(TASK_INTERRUPTIBLE);
1342 spin_unlock_irqrestore(&s->lock, flags);
1343 if(cnt > count)
1344  cnt = count;
1345 if(cnt <=0) {
1346 start_adc(s);
1347 if(file->f_flags & O_NONBLOCK) {
1348 if(!ret)
1349  ret = -EAGAIN;
1350 break;
1351 }
1352 if(!schedule_timeout(HZ)) {
1353 printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1354  s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1355  s->dma_adc.hwptr, s->dma_adc.swptr);
1356 stop_adc(s);
1357 spin_lock_irqsave(&s->lock, flags);
1358 set_dmac(s,virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1359 /* program enhanced mode registers */
1360 wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >>8);
1361 wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
1362  s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr =0;
1363 spin_unlock_irqrestore(&s->lock, flags);
1364 }
1365 if(signal_pending(current)) {
1366 if(!ret)
1367  ret = -ERESTARTSYS;
1368 break;
1369 }
1370 continue;
1371 }
1372 if(copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1373 if(!ret)
1374  ret = -EFAULT;
1375 break;
1376 }
1377  swptr = (swptr + cnt) % s->dma_adc.dmasize;
1378 spin_lock_irqsave(&s->lock, flags);
1379  s->dma_adc.swptr = swptr;
1380  s->dma_adc.count -= cnt;
1381 spin_unlock_irqrestore(&s->lock, flags);
1382  count -= cnt;
1383  buffer += cnt;
1384  ret += cnt;
1385 start_adc(s);
1386 }
1387 remove_wait_queue(&s->dma_adc.wait, &wait);
1388 set_current_state(TASK_RUNNING);
1389 return ret;
1390 }
1391
1392 static ssize_t sv_write(struct file *file,const char*buffer,size_t count, loff_t *ppos)
1393 {
1394 struct sv_state *s = (struct sv_state *)file->private_data;
1395 DECLARE_WAITQUEUE(wait, current);
1396  ssize_t ret;
1397 unsigned long flags;
1398 unsigned swptr;
1399 int cnt;
1400
1401 VALIDATE_STATE(s);
1402 if(ppos != &file->f_pos)
1403 return-ESPIPE;
1404 if(s->dma_dac.mapped)
1405 return-ENXIO;
1406 if(!s->dma_dac.ready && (ret =prog_dmabuf(s,0)))
1407 return ret;
1408 if(!access_ok(VERIFY_READ, buffer, count))
1409 return-EFAULT;
1410  ret =0;
1411 #if 0
1412 spin_lock_irqsave(&s->lock, flags);
1413 sv_update_ptr(s);
1414 spin_unlock_irqrestore(&s->lock, flags);
1415 #endif
1416 add_wait_queue(&s->dma_dac.wait, &wait);
1417 while(count >0) {
1418 spin_lock_irqsave(&s->lock, flags);
1419 if(s->dma_dac.count <0) {
1420  s->dma_dac.count =0;
1421  s->dma_dac.swptr = s->dma_dac.hwptr;
1422 }
1423  swptr = s->dma_dac.swptr;
1424  cnt = s->dma_dac.dmasize-swptr;
1425 if(s->dma_dac.count + cnt > s->dma_dac.dmasize)
1426  cnt = s->dma_dac.dmasize - s->dma_dac.count;
1427 if(cnt <=0)
1428 __set_current_state(TASK_INTERRUPTIBLE);
1429 spin_unlock_irqrestore(&s->lock, flags);
1430 if(cnt > count)
1431  cnt = count;
1432 if(cnt <=0) {
1433 start_dac(s);
1434 if(file->f_flags & O_NONBLOCK) {
1435 if(!ret)
1436  ret = -EAGAIN;
1437 break;
1438 }
1439 if(!schedule_timeout(HZ)) {
1440 printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1441  s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1442  s->dma_dac.hwptr, s->dma_dac.swptr);
1443 stop_dac(s);
1444 spin_lock_irqsave(&s->lock, flags);
1445 set_dmaa(s,virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1446 /* program enhanced mode registers */
1447 wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >>8);
1448 wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
1449  s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr =0;
1450 spin_unlock_irqrestore(&s->lock, flags);
1451 }
1452 if(signal_pending(current)) {
1453 if(!ret)
1454  ret = -ERESTARTSYS;
1455 break;
1456 }
1457 continue;
1458 }
1459 if(copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1460 if(!ret)
1461  ret = -EFAULT;
1462 break;
1463 }
1464  swptr = (swptr + cnt) % s->dma_dac.dmasize;
1465 spin_lock_irqsave(&s->lock, flags);
1466  s->dma_dac.swptr = swptr;
1467  s->dma_dac.count += cnt;
1468  s->dma_dac.endcleared =0;
1469 spin_unlock_irqrestore(&s->lock, flags);
1470  count -= cnt;
1471  buffer += cnt;
1472  ret += cnt;
1473 start_dac(s);
1474 }
1475 remove_wait_queue(&s->dma_dac.wait, &wait);
1476 set_current_state(TASK_RUNNING);
1477 return ret;
1478 }
1479
1480 /* No kernel lock - we have our own spinlock */
1481 static unsigned intsv_poll(struct file *file,struct poll_table_struct *wait)
1482 {
1483 struct sv_state *s = (struct sv_state *)file->private_data;
1484 unsigned long flags;
1485 unsigned int mask =0;
1486
1487 VALIDATE_STATE(s);
1488 if(file->f_mode & FMODE_WRITE) {
1489 if(!s->dma_dac.ready &&prog_dmabuf(s,1))
1490 return0;
1491 poll_wait(file, &s->dma_dac.wait, wait);
1492 }
1493 if(file->f_mode & FMODE_READ) {
1494 if(!s->dma_adc.ready &&prog_dmabuf(s,0))
1495 return0;
1496 poll_wait(file, &s->dma_adc.wait, wait);
1497 }
1498 spin_lock_irqsave(&s->lock, flags);
1499 sv_update_ptr(s);
1500 if(file->f_mode & FMODE_READ) {
1501 if(s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1502  mask |= POLLIN | POLLRDNORM;
1503 }
1504 if(file->f_mode & FMODE_WRITE) {
1505 if(s->dma_dac.mapped) {
1506 if(s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1507  mask |= POLLOUT | POLLWRNORM;
1508 }else{
1509 if((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1510  mask |= POLLOUT | POLLWRNORM;
1511 }
1512 }
1513 spin_unlock_irqrestore(&s->lock, flags);
1514 return mask;
1515 }
1516
1517 static intsv_mmap(struct file *file,struct vm_area_struct *vma)
1518 {
1519 struct sv_state *s = (struct sv_state *)file->private_data;
1520 struct dmabuf *db;
1521 int ret = -EINVAL;
1522 unsigned long size;
1523
1524 VALIDATE_STATE(s);
1525 lock_kernel();
1526 if(vma->vm_flags & VM_WRITE) {
1527 if((ret =prog_dmabuf(s,1)) !=0)
1528 goto out;
1529  db = &s->dma_dac;
1530 }else if(vma->vm_flags & VM_READ) {
1531 if((ret =prog_dmabuf(s,0)) !=0)
1532 goto out;
1533  db = &s->dma_adc;
1534 }else
1535 goto out;
1536  ret = -EINVAL;
1537 if(vma->vm_pgoff !=0)
1538 goto out;
1539  size = vma->vm_end - vma->vm_start;
1540 if(size > (PAGE_SIZE << db->buforder))
1541 goto out;
1542  ret = -EAGAIN;
1543 if(remap_page_range(vma->vm_start,virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1544 goto out;
1545  db->mapped =1;
1546  ret =0;
1547 out:
1548 unlock_kernel();
1549 return ret;
1550 }
1551
1552 static intsv_ioctl(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
1553 {
1554 struct sv_state *s = (struct sv_state *)file->private_data;
1555 unsigned long flags;
1556  audio_buf_info abinfo;
1557  count_info cinfo;
1558 int count;
1559 int val, mapped, ret;
1560 unsigned char fmtm, fmtd;
1561
1562 VALIDATE_STATE(s);
1563  mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1564 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1565 switch(cmd) {
1566 case OSS_GETVERSION:
1567 returnput_user(SOUND_VERSION, (int*)arg);
1568
1569 case SNDCTL_DSP_SYNC:
1570 if(file->f_mode & FMODE_WRITE)
1571 returndrain_dac(s,0/*file->f_flags & O_NONBLOCK*/);
1572 return0;
1573
1574 case SNDCTL_DSP_SETDUPLEX:
1575 return0;
1576
1577 case SNDCTL_DSP_GETCAPS:
1578 returnput_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int*)arg);
1579
1580 case SNDCTL_DSP_RESET:
1581 if(file->f_mode & FMODE_WRITE) {
1582 stop_dac(s);
1583 synchronize_irq();
1584  s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes =0;
1585 }
1586 if(file->f_mode & FMODE_READ) {
1587 stop_adc(s);
1588 synchronize_irq();
1589  s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes =0;
1590 }
1591 return0;
1592
1593 case SNDCTL_DSP_SPEED:
1594 if(get_user(val, (int*)arg))
1595 return-EFAULT;
1596 if(val >=0) {
1597 if(file->f_mode & FMODE_READ) {
1598 stop_adc(s);
1599  s->dma_adc.ready =0;
1600 set_adc_rate(s, val);
1601 }
1602 if(file->f_mode & FMODE_WRITE) {
1603 stop_dac(s);
1604  s->dma_dac.ready =0;
1605 set_dac_rate(s, val);
1606 }
1607 }
1608 returnput_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int*)arg);
1609
1610 case SNDCTL_DSP_STEREO:
1611 if(get_user(val, (int*)arg))
1612 return-EFAULT;
1613  fmtd =0;
1614  fmtm = ~0;
1615 if(file->f_mode & FMODE_READ) {
1616 stop_adc(s);
1617  s->dma_adc.ready =0;
1618 if(val)
1619  fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1620 else
1621  fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1622 }
1623 if(file->f_mode & FMODE_WRITE) {
1624 stop_dac(s);
1625  s->dma_dac.ready =0;
1626 if(val)
1627  fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1628 else
1629  fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1630 }
1631 set_fmt(s, fmtm, fmtd);
1632 return0;
1633
1634 case SNDCTL_DSP_CHANNELS:
1635 if(get_user(val, (int*)arg))
1636 return-EFAULT;
1637 if(val !=0) {
1638  fmtd =0;
1639  fmtm = ~0;
1640 if(file->f_mode & FMODE_READ) {
1641 stop_adc(s);
1642  s->dma_adc.ready =0;
1643 if(val >=2)
1644  fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1645 else
1646  fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1647 }
1648 if(file->f_mode & FMODE_WRITE) {
1649 stop_dac(s);
1650  s->dma_dac.ready =0;
1651 if(val >=2)
1652  fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1653 else
1654  fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1655 }
1656 set_fmt(s, fmtm, fmtd);
1657 }
1658 returnput_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1659 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ?2:1, (int*)arg);
1660
1661 case SNDCTL_DSP_GETFMTS:/* Returns a mask */
1662 returnput_user(AFMT_S16_LE|AFMT_U8, (int*)arg);
1663
1664 case SNDCTL_DSP_SETFMT:/* Selects ONE fmt*/
1665 if(get_user(val, (int*)arg))
1666 return-EFAULT;
1667 if(val != AFMT_QUERY) {
1668  fmtd =0;
1669  fmtm = ~0;
1670 if(file->f_mode & FMODE_READ) {
1671 stop_adc(s);
1672  s->dma_adc.ready =0;
1673 if(val == AFMT_S16_LE)
1674  fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1675 else
1676  fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
1677 }
1678 if(file->f_mode & FMODE_WRITE) {
1679 stop_dac(s);
1680  s->dma_dac.ready =0;
1681 if(val == AFMT_S16_LE)
1682  fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1683 else
1684  fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
1685 }
1686 set_fmt(s, fmtm, fmtd);
1687 }
1688 returnput_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1689 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, (int*)arg);
1690
1691 case SNDCTL_DSP_POST:
1692 return0;
1693
1694 case SNDCTL_DSP_GETTRIGGER:
1695  val =0;
1696 if(file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
1697  val |= PCM_ENABLE_INPUT;
1698 if(file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
1699  val |= PCM_ENABLE_OUTPUT;
1700 returnput_user(val, (int*)arg);
1701
1702 case SNDCTL_DSP_SETTRIGGER:
1703 if(get_user(val, (int*)arg))
1704 return-EFAULT;
1705 if(file->f_mode & FMODE_READ) {
1706 if(val & PCM_ENABLE_INPUT) {
1707 if(!s->dma_adc.ready && (ret =prog_dmabuf(s,1)))
1708 return ret;
1709 start_adc(s);
1710 }else
1711 stop_adc(s);
1712 }
1713 if(file->f_mode & FMODE_WRITE) {
1714 if(val & PCM_ENABLE_OUTPUT) {
1715 if(!s->dma_dac.ready && (ret =prog_dmabuf(s,0)))
1716 return ret;
1717 start_dac(s);
1718 }else
1719 stop_dac(s);
1720 }
1721 return0;
1722
1723 case SNDCTL_DSP_GETOSPACE:
1724 if(!(file->f_mode & FMODE_WRITE))
1725 return-EINVAL;
1726 if(!s->dma_dac.ready && (ret =prog_dmabuf(s,0)))
1727 return ret;
1728 spin_lock_irqsave(&s->lock, flags);
1729 sv_update_ptr(s);
1730  abinfo.fragsize = s->dma_dac.fragsize;
1731  count = s->dma_dac.count;
1732 if(count <0)
1733  count =0;
1734  abinfo.bytes = s->dma_dac.dmasize - count;
1735  abinfo.fragstotal = s->dma_dac.numfrag;
1736  abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1737 spin_unlock_irqrestore(&s->lock, flags);
1738 returncopy_to_user((void*)arg, &abinfo,sizeof(abinfo)) ? -EFAULT :0;
1739
1740 case SNDCTL_DSP_GETISPACE:
1741 if(!(file->f_mode & FMODE_READ))
1742 return-EINVAL;
1743 if(!s->dma_adc.ready && (ret =prog_dmabuf(s,1)))
1744 return ret;
1745 spin_lock_irqsave(&s->lock, flags);
1746 sv_update_ptr(s);
1747  abinfo.fragsize = s->dma_adc.fragsize;
1748  count = s->dma_adc.count;
1749 if(count <0)
1750  count =0;
1751  abinfo.bytes = count;
1752  abinfo.fragstotal = s->dma_adc.numfrag;
1753  abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1754 spin_unlock_irqrestore(&s->lock, flags);
1755 returncopy_to_user((void*)arg, &abinfo,sizeof(abinfo)) ? -EFAULT :0;
1756
1757 case SNDCTL_DSP_NONBLOCK:
1758  file->f_flags |= O_NONBLOCK;
1759 return0;
1760
1761 case SNDCTL_DSP_GETODELAY:
1762 if(!(file->f_mode & FMODE_WRITE))
1763 return-EINVAL;
1764 if(!s->dma_dac.ready && (ret =prog_dmabuf(s,0)))
1765 return ret;
1766 spin_lock_irqsave(&s->lock, flags);
1767 sv_update_ptr(s);
1768  count = s->dma_dac.count;
1769 spin_unlock_irqrestore(&s->lock, flags);
1770 if(count <0)
1771  count =0;
1772 returnput_user(count, (int*)arg);
1773
1774 case SNDCTL_DSP_GETIPTR:
1775 if(!(file->f_mode & FMODE_READ))
1776 return-EINVAL;
1777 if(!s->dma_adc.ready && (ret =prog_dmabuf(s,1)))
1778 return ret;
1779 spin_lock_irqsave(&s->lock, flags);
1780 sv_update_ptr(s);
1781  cinfo.bytes = s->dma_adc.total_bytes;
1782  count = s->dma_adc.count;
1783 if(count <0)
1784  count =0;
1785  cinfo.blocks = count >> s->dma_adc.fragshift;
1786  cinfo.ptr = s->dma_adc.hwptr;
1787 if(s->dma_adc.mapped)
1788  s->dma_adc.count &= s->dma_adc.fragsize-1;
1789 spin_unlock_irqrestore(&s->lock, flags);
1790 returncopy_to_user((void*)arg, &cinfo,sizeof(cinfo));
1791
1792 case SNDCTL_DSP_GETOPTR:
1793 if(!(file->f_mode & FMODE_WRITE))
1794 return-EINVAL;
1795 if(!s->dma_dac.ready && (ret =prog_dmabuf(s,0)))
1796 return ret;
1797 spin_lock_irqsave(&s->lock, flags);
1798 sv_update_ptr(s);
1799  cinfo.bytes = s->dma_dac.total_bytes;
1800  count = s->dma_dac.count;
1801 if(count <0)
1802  count =0;
1803  cinfo.blocks = count >> s->dma_dac.fragshift;
1804  cinfo.ptr = s->dma_dac.hwptr;
1805 if(s->dma_dac.mapped)
1806  s->dma_dac.count &= s->dma_dac.fragsize-1;
1807 spin_unlock_irqrestore(&s->lock, flags);
1808 returncopy_to_user((void*)arg, &cinfo,sizeof(cinfo));
1809
1810 case SNDCTL_DSP_GETBLKSIZE:
1811 if(file->f_mode & FMODE_WRITE) {
1812 if((val =prog_dmabuf(s,0)))
1813 return val;
1814 returnput_user(s->dma_dac.fragsize, (int*)arg);
1815 }
1816 if((val =prog_dmabuf(s,1)))
1817 return val;
1818 returnput_user(s->dma_adc.fragsize, (int*)arg);
1819
1820 case SNDCTL_DSP_SETFRAGMENT:
1821 if(get_user(val, (int*)arg))
1822 return-EFAULT;
1823 if(file->f_mode & FMODE_READ) {
1824  s->dma_adc.ossfragshift = val &0xffff;
1825  s->dma_adc.ossmaxfrags = (val >>16) &0xffff;
1826 if(s->dma_adc.ossfragshift <4)
1827  s->dma_adc.ossfragshift =4;
1828 if(s->dma_adc.ossfragshift >15)
1829  s->dma_adc.ossfragshift =15;
1830 if(s->dma_adc.ossmaxfrags <4)
1831  s->dma_adc.ossmaxfrags =4;
1832 }
1833 if(file->f_mode & FMODE_WRITE) {
1834  s->dma_dac.ossfragshift = val &0xffff;
1835  s->dma_dac.ossmaxfrags = (val >>16) &0xffff;
1836 if(s->dma_dac.ossfragshift <4)
1837  s->dma_dac.ossfragshift =4;
1838 if(s->dma_dac.ossfragshift >15)
1839  s->dma_dac.ossfragshift =15;
1840 if(s->dma_dac.ossmaxfrags <4)
1841  s->dma_dac.ossmaxfrags =4;
1842 }
1843 return0;
1844
1845 case SNDCTL_DSP_SUBDIVIDE:
1846 if((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1847 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1848 return-EINVAL;
1849 if(get_user(val, (int*)arg))
1850 return-EFAULT;
1851 if(val !=1&& val !=2&& val !=4)
1852 return-EINVAL;
1853 if(file->f_mode & FMODE_READ)
1854  s->dma_adc.subdivision = val;
1855 if(file->f_mode & FMODE_WRITE)
1856  s->dma_dac.subdivision = val;
1857 return0;
1858
1859 case SOUND_PCM_READ_RATE:
1860 returnput_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, (int*)arg);
1861
1862 case SOUND_PCM_READ_CHANNELS:
1863 returnput_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1864 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ?2:1, (int*)arg);
1865
1866 case SOUND_PCM_READ_BITS:
1867 returnput_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1868 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ?16:8, (int*)arg);
1869
1870 case SOUND_PCM_WRITE_FILTER:
1871 case SNDCTL_DSP_SETSYNCRO:
1872 case SOUND_PCM_READ_FILTER:
1873 return-EINVAL;
1874
1875 }
1876 returnmixer_ioctl(s, cmd, arg);
1877 }
1878
1879 static intsv_open(struct inode *inode,struct file *file)
1880 {
1881 int minor =MINOR(inode->i_rdev);
1882 DECLARE_WAITQUEUE(wait, current);
1883 unsigned char fmtm = ~0, fmts =0;
1884 struct list_head *list;
1885 struct sv_state *s;
1886
1887 for(list = devs.next; ; list = list->next) {
1888 if(list == &devs)
1889 return-ENODEV;
1890  s =list_entry(list,struct sv_state, devs);
1891 if(!((s->dev_audio ^ minor) & ~0xf))
1892 break;
1893 }
1894 VALIDATE_STATE(s);
1895  file->private_data = s;
1896 /* wait for device to become free */
1897 down(&s->open_sem);
1898 while(s->open_mode & file->f_mode) {
1899 if(file->f_flags & O_NONBLOCK) {
1900 up(&s->open_sem);
1901 return-EBUSY;
1902 }
1903 add_wait_queue(&s->open_wait, &wait);
1904 __set_current_state(TASK_INTERRUPTIBLE);
1905 up(&s->open_sem);
1906 schedule();
1907 remove_wait_queue(&s->open_wait, &wait);
1908 set_current_state(TASK_RUNNING);
1909 if(signal_pending(current))
1910 return-ERESTARTSYS;
1911 down(&s->open_sem);
1912 }
1913 if(file->f_mode & FMODE_READ) {
1914  fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
1915 if((minor &0xf) == SND_DEV_DSP16)
1916  fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1917  s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision =0;
1918 set_adc_rate(s,8000);
1919 }
1920 if(file->f_mode & FMODE_WRITE) {
1921  fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
1922 if((minor &0xf) == SND_DEV_DSP16)
1923  fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1924  s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision =0;
1925 set_dac_rate(s,8000);
1926 }
1927 set_fmt(s, fmtm, fmts);
1928  s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1929 up(&s->open_sem);
1930 return0;
1931 }
1932
1933 static intsv_release(struct inode *inode,struct file *file)
1934 {
1935 struct sv_state *s = (struct sv_state *)file->private_data;
1936
1937 VALIDATE_STATE(s);
1938 lock_kernel();
1939 if(file->f_mode & FMODE_WRITE)
1940 drain_dac(s, file->f_flags & O_NONBLOCK);
1941 down(&s->open_sem);
1942 if(file->f_mode & FMODE_WRITE) {
1943 stop_dac(s);
1944 dealloc_dmabuf(s, &s->dma_dac);
1945 }
1946 if(file->f_mode & FMODE_READ) {
1947 stop_adc(s);
1948 dealloc_dmabuf(s, &s->dma_adc);
1949 }
1950  s->open_mode &= (~file->f_mode) & (FMODE_READ|FMODE_WRITE);
1951 wake_up(&s->open_wait);
1952 up(&s->open_sem);
1953 unlock_kernel();
1954 return0;
1955 }
1956
1957 static/*const*/struct file_operations sv_audio_fops = {
1958  owner: THIS_MODULE,
1959  llseek: sv_llseek,
1960  read: sv_read,
1961  write: sv_write,
1962  poll: sv_poll,
1963  ioctl: sv_ioctl,
1964  mmap: sv_mmap,
1965  open: sv_open,
1966  release: sv_release,
1967 };
1968
1969 /* --------------------------------------------------------------------- */
1970
1971 static ssize_t sv_midi_read(struct file *file,char*buffer,size_t count, loff_t *ppos)
1972 {
1973 struct sv_state *s = (struct sv_state *)file->private_data;
1974 DECLARE_WAITQUEUE(wait, current);
1975  ssize_t ret;
1976 unsigned long flags;
1977 unsigned ptr;
1978 int cnt;
1979
1980 VALIDATE_STATE(s);
1981 if(ppos != &file->f_pos)
1982 return-ESPIPE;
1983 if(!access_ok(VERIFY_WRITE, buffer, count))
1984 return-EFAULT;
1985 if(count ==0)
1986 return0;
1987  ret =0;
1988 add_wait_queue(&s->midi.iwait, &wait);
1989 while(count >0) {
1990 spin_lock_irqsave(&s->lock, flags);
1991  ptr = s->midi.ird;
1992  cnt = MIDIINBUF - ptr;
1993 if(s->midi.icnt < cnt)
1994  cnt = s->midi.icnt;
1995 if(cnt <=0)
1996 __set_current_state(TASK_INTERRUPTIBLE);
1997 spin_unlock_irqrestore(&s->lock, flags);
1998 if(cnt > count)
1999  cnt = count;
2000 if(cnt <=0) {
2001 if(file->f_flags & O_NONBLOCK) {
2002 if(!ret)
2003  ret = -EAGAIN;
2004 break;
2005 }
2006 schedule();
2007 if(signal_pending(current)) {
2008 if(!ret)
2009  ret = -ERESTARTSYS;
2010 break;
2011 }
2012 continue;
2013 }
2014 if(copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2015 if(!ret)
2016  ret = -EFAULT;
2017 break;
2018 }
2019  ptr = (ptr + cnt) % MIDIINBUF;
2020 spin_lock_irqsave(&s->lock, flags);
2021  s->midi.ird = ptr;
2022  s->midi.icnt -= cnt;
2023 spin_unlock_irqrestore(&s->lock, flags);
2024  count -= cnt;
2025  buffer += cnt;
2026  ret += cnt;
2027 break;
2028 }
2029 __set_current_state(TASK_RUNNING);
2030 remove_wait_queue(&s->midi.iwait, &wait);
2031 return ret;
2032 }
2033
2034 static ssize_t sv_midi_write(struct file *file,const char*buffer,size_t count, loff_t *ppos)
2035 {
2036 struct sv_state *s = (struct sv_state *)file->private_data;
2037 DECLARE_WAITQUEUE(wait, current);
2038  ssize_t ret;
2039 unsigned long flags;
2040 unsigned ptr;
2041 int cnt;
2042
2043 VALIDATE_STATE(s);
2044 if(ppos != &file->f_pos)
2045 return-ESPIPE;
2046 if(!access_ok(VERIFY_READ, buffer, count))
2047 return-EFAULT;
2048 if(count ==0)
2049 return0;
2050  ret =0;
2051 add_wait_queue(&s->midi.owait, &wait);
2052 while(count >0) {
2053 spin_lock_irqsave(&s->lock, flags);
2054  ptr = s->midi.owr;
2055  cnt = MIDIOUTBUF - ptr;
2056 if(s->midi.ocnt + cnt > MIDIOUTBUF)
2057  cnt = MIDIOUTBUF - s->midi.ocnt;
2058 if(cnt <=0) {
2059 __set_current_state(TASK_INTERRUPTIBLE);
2060 sv_handle_midi(s);
2061 }
2062 spin_unlock_irqrestore(&s->lock, flags);
2063 if(cnt > count)
2064  cnt = count;
2065 if(cnt <=0) {
2066 if(file->f_flags & O_NONBLOCK) {
2067 if(!ret)
2068  ret = -EAGAIN;
2069 break;
2070 }
2071 schedule();
2072 if(signal_pending(current)) {
2073 if(!ret)
2074  ret = -ERESTARTSYS;
2075 break;
2076 }
2077 continue;
2078 }
2079 if(copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2080 if(!ret)
2081  ret = -EFAULT;
2082 break;
2083 }
2084  ptr = (ptr + cnt) % MIDIOUTBUF;
2085 spin_lock_irqsave(&s->lock, flags);
2086  s->midi.owr = ptr;
2087  s->midi.ocnt += cnt;
2088 spin_unlock_irqrestore(&s->lock, flags);
2089  count -= cnt;
2090  buffer += cnt;
2091  ret += cnt;
2092 spin_lock_irqsave(&s->lock, flags);
2093 sv_handle_midi(s);
2094 spin_unlock_irqrestore(&s->lock, flags);
2095 }
2096 __set_current_state(TASK_RUNNING);
2097 remove_wait_queue(&s->midi.owait, &wait);
2098 return ret;
2099 }
2100
2101 /* No kernel lock - we have our own spinlock */
2102 static unsigned intsv_midi_poll(struct file *file,struct poll_table_struct *wait)
2103 {
2104 struct sv_state *s = (struct sv_state *)file->private_data;
2105 unsigned long flags;
2106 unsigned int mask =0;
2107
2108 VALIDATE_STATE(s);
2109 if(file->f_mode & FMODE_WRITE)
2110 poll_wait(file, &s->midi.owait, wait);
2111 if(file->f_mode & FMODE_READ)
2112 poll_wait(file, &s->midi.iwait, wait);
2113 spin_lock_irqsave(&s->lock, flags);
2114 if(file->f_mode & FMODE_READ) {
2115 if(s->midi.icnt >0)
2116  mask |= POLLIN | POLLRDNORM;
2117 }
2118 if(file->f_mode & FMODE_WRITE) {
2119 if(s->midi.ocnt < MIDIOUTBUF)
2120  mask |= POLLOUT | POLLWRNORM;
2121 }
2122 spin_unlock_irqrestore(&s->lock, flags);
2123 return mask;
2124 }
2125
2126 static intsv_midi_open(struct inode *inode,struct file *file)
2127 {
2128 int minor =MINOR(inode->i_rdev);
2129 DECLARE_WAITQUEUE(wait, current);
2130 unsigned long flags;
2131 struct list_head *list;
2132 struct sv_state *s;
2133
2134 for(list = devs.next; ; list = list->next) {
2135 if(list == &devs)
2136 return-ENODEV;
2137  s =list_entry(list,struct sv_state, devs);
2138 if(s->dev_midi == minor)
2139 break;
2140 }
2141 VALIDATE_STATE(s);
2142  file->private_data = s;
2143 /* wait for device to become free */
2144 down(&s->open_sem);
2145 while(s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2146 if(file->f_flags & O_NONBLOCK) {
2147 up(&s->open_sem);
2148 return-EBUSY;
2149 }
2150 add_wait_queue(&s->open_wait, &wait);
2151 __set_current_state(TASK_INTERRUPTIBLE);
2152 up(&s->open_sem);
2153 schedule();
2154 remove_wait_queue(&s->open_wait, &wait);
2155 set_current_state(TASK_RUNNING);
2156 if(signal_pending(current))
2157 return-ERESTARTSYS;
2158 down(&s->open_sem);
2159 }
2160 spin_lock_irqsave(&s->lock, flags);
2161 if(!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2162  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
2163  s->midi.ord = s->midi.owr = s->midi.ocnt =0;
2164 //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
2165 outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2166 wrindir(s, SV_CIUARTCONTROL,5);/* output MIDI data to external and internal synth */
2167 wrindir(s, SV_CIWAVETABLESRC,1);/* Wavetable in PC RAM */
2168 outb(0xff, s->iomidi+1);/* reset command */
2169 outb(0x3f, s->iomidi+1);/* uart command */
2170 if(!(inb(s->iomidi+1) &0x80))
2171 inb(s->iomidi);
2172  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
2173 init_timer(&s->midi.timer);
2174  s->midi.timer.expires = jiffies+1;
2175  s->midi.timer.data = (unsigned long)s;
2176  s->midi.timer.function = sv_midi_timer;
2177 add_timer(&s->midi.timer);
2178 }
2179 if(file->f_mode & FMODE_READ) {
2180  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
2181 }
2182 if(file->f_mode & FMODE_WRITE) {
2183  s->midi.ord = s->midi.owr = s->midi.ocnt =0;
2184 }
2185 spin_unlock_irqrestore(&s->lock, flags);
2186  s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2187 up(&s->open_sem);
2188 return0;
2189 }
2190
2191 static intsv_midi_release(struct inode *inode,struct file *file)
2192 {
2193 struct sv_state *s = (struct sv_state *)file->private_data;
2194 DECLARE_WAITQUEUE(wait, current);
2195 unsigned long flags;
2196 unsigned count, tmo;
2197
2198 VALIDATE_STATE(s);
2199
2200 lock_kernel();
2201 if(file->f_mode & FMODE_WRITE) {
2202 add_wait_queue(&s->midi.owait, &wait);
2203 for(;;) {
2204 __set_current_state(TASK_INTERRUPTIBLE);
2205 spin_lock_irqsave(&s->lock, flags);
2206  count = s->midi.ocnt;
2207 spin_unlock_irqrestore(&s->lock, flags);
2208 if(count <=0)
2209 break;
2210 if(signal_pending(current))
2211 break;
2212 if(file->f_flags & O_NONBLOCK) {
2213 remove_wait_queue(&s->midi.owait, &wait);
2214 set_current_state(TASK_RUNNING);
2215 return-EBUSY;
2216 }
2217  tmo = (count * HZ) /3100;
2218 if(!schedule_timeout(tmo ? :1) && tmo)
2219 printk(KERN_DEBUG "sv: midi timed out??\n");
2220 }
2221 remove_wait_queue(&s->midi.owait, &wait);
2222 set_current_state(TASK_RUNNING);
2223 }
2224 down(&s->open_sem);
2225  s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
2226 spin_lock_irqsave(&s->lock, flags);
2227 if(!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2228 outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2229 del_timer(&s->midi.timer);
2230 }
2231 spin_unlock_irqrestore(&s->lock, flags);
2232 wake_up(&s->open_wait);
2233 up(&s->open_sem);
2234 unlock_kernel();
2235 return0;
2236 }
2237
2238 static/*const*/struct file_operations sv_midi_fops = {
2239  owner: THIS_MODULE,
2240  llseek: sv_llseek,
2241  read: sv_midi_read,
2242  write: sv_midi_write,
2243  poll: sv_midi_poll,
2244  open: sv_midi_open,
2245  release: sv_midi_release,
2246 };
2247
2248 /* --------------------------------------------------------------------- */
2249
2250 static intsv_dmfm_ioctl(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
2251 {
2252 static const unsigned char op_offset[18] = {
2253 0x00,0x01,0x02,0x03,0x04,0x05,
2254 0x08,0x09,0x0A,0x0B,0x0C,0x0D,
2255 0x10,0x11,0x12,0x13,0x14,0x15
2256 };
2257 struct sv_state *s = (struct sv_state *)file->private_data;
2258 struct dm_fm_voice v;
2259 struct dm_fm_note n;
2260 struct dm_fm_params p;
2261 unsigned int io;
2262 unsigned int regb;
2263
2264 switch(cmd) {
2265 case FM_IOCTL_RESET:
2266 for(regb =0xb0; regb <0xb9; regb++) {
2267 outb(regb, s->iosynth);
2268 outb(0, s->iosynth+1);
2269 outb(regb, s->iosynth+2);
2270 outb(0, s->iosynth+3);
2271 }
2272 return0;
2273
2274 case FM_IOCTL_PLAY_NOTE:
2275 if(copy_from_user(&n, (void*)arg,sizeof(n)))
2276 return-EFAULT;
2277 if(n.voice >=18)
2278 return-EINVAL;
2279 if(n.voice >=9) {
2280  regb = n.voice -9;
2281  io = s->iosynth+2;
2282 }else{
2283  regb = n.voice;
2284  io = s->iosynth;
2285 }
2286 outb(0xa0+ regb, io);
2287 outb(n.fnum &0xff, io+1);
2288 outb(0xb0+ regb, io);
2289 outb(((n.fnum >>8) &3) | ((n.octave &7) <<2) | ((n.key_on &1) <<5), io+1);
2290 return0;
2291
2292 case FM_IOCTL_SET_VOICE:
2293 if(copy_from_user(&v, (void*)arg,sizeof(v)))
2294 return-EFAULT;
2295 if(v.voice >=18)
2296 return-EINVAL;
2297  regb = op_offset[v.voice];
2298  io = s->iosynth + ((v.op &1) <<1);
2299 outb(0x20+ regb, io);
2300 outb(((v.am &1) <<7) | ((v.vibrato &1) <<6) | ((v.do_sustain &1) <<5) |
2301 ((v.kbd_scale &1) <<4) | (v.harmonic &0xf), io+1);
2302 outb(0x40+ regb, io);
2303 outb(((v.scale_level &0x3) <<6) | (v.volume &0x3f), io+1);
2304 outb(0x60+ regb, io);
2305 outb(((v.attack &0xf) <<4) | (v.decay &0xf), io+1);
2306 outb(0x80+ regb, io);
2307 outb(((v.sustain &0xf) <<4) | (v.release &0xf), io+1);
2308 outb(0xe0+ regb, io);
2309 outb(v.waveform &0x7, io+1);
2310 if(n.voice >=9) {
2311  regb = n.voice -9;
2312  io = s->iosynth+2;
2313 }else{
2314  regb = n.voice;
2315  io = s->iosynth;
2316 }
2317 outb(0xc0+ regb, io);
2318 outb(((v.right &1) <<5) | ((v.left &1) <<4) | ((v.feedback &7) <<1) |
2319 (v.connection &1), io+1);
2320 return0;
2321
2322 case FM_IOCTL_SET_PARAMS:
2323 if(copy_from_user(&p, (void*)arg,sizeof(p)))
2324 return-EFAULT;
2325 outb(0x08, s->iosynth);
2326 outb((p.kbd_split &1) <<6, s->iosynth+1);
2327 outb(0xbd, s->iosynth);
2328 outb(((p.am_depth &1) <<7) | ((p.vib_depth &1) <<6) | ((p.rhythm &1) <<5) | ((p.bass &1) <<4) |
2329 ((p.snare &1) <<3) | ((p.tomtom &1) <<2) | ((p.cymbal &1) <<1) | (p.hihat &1), s->iosynth+1);
2330 return0;
2331
2332 case FM_IOCTL_SET_OPL:
2333 outb(4, s->iosynth+2);
2334 outb(arg, s->iosynth+3);
2335 return0;
2336
2337 case FM_IOCTL_SET_MODE:
2338 outb(5, s->iosynth+2);
2339 outb(arg &1, s->iosynth+3);
2340 return0;
2341
2342 default:
2343 return-EINVAL;
2344 }
2345 }
2346
2347 static intsv_dmfm_open(struct inode *inode,struct file *file)
2348 {
2349 int minor =MINOR(inode->i_rdev);
2350 DECLARE_WAITQUEUE(wait, current);
2351 struct list_head *list;
2352 struct sv_state *s;
2353
2354 for(list = devs.next; ; list = list->next) {
2355 if(list == &devs)
2356 return-ENODEV;
2357  s =list_entry(list,struct sv_state, devs);
2358 if(s->dev_dmfm == minor)
2359 break;
2360 }
2361 VALIDATE_STATE(s);
2362  file->private_data = s;
2363 /* wait for device to become free */
2364 down(&s->open_sem);
2365 while(s->open_mode & FMODE_DMFM) {
2366 if(file->f_flags & O_NONBLOCK) {
2367 up(&s->open_sem);
2368 return-EBUSY;
2369 }
2370 add_wait_queue(&s->open_wait, &wait);
2371 __set_current_state(TASK_INTERRUPTIBLE);
2372 up(&s->open_sem);
2373 schedule();
2374 remove_wait_queue(&s->open_wait, &wait);
2375 set_current_state(TASK_RUNNING);
2376 if(signal_pending(current))
2377 return-ERESTARTSYS;
2378 down(&s->open_sem);
2379 }
2380 /* init the stuff */
2381 outb(1, s->iosynth);
2382 outb(0x20, s->iosynth+1);/* enable waveforms */
2383 outb(4, s->iosynth+2);
2384 outb(0, s->iosynth+3);/* no 4op enabled */
2385 outb(5, s->iosynth+2);
2386 outb(1, s->iosynth+3);/* enable OPL3 */
2387  s->open_mode |= FMODE_DMFM;
2388 up(&s->open_sem);
2389 return0;
2390 }
2391
2392 static intsv_dmfm_release(struct inode *inode,struct file *file)
2393 {
2394 struct sv_state *s = (struct sv_state *)file->private_data;
2395 unsigned int regb;
2396
2397 VALIDATE_STATE(s);
2398 lock_kernel();
2399 down(&s->open_sem);
2400  s->open_mode &= ~FMODE_DMFM;
2401 for(regb =0xb0; regb <0xb9; regb++) {
2402 outb(regb, s->iosynth);
2403 outb(0, s->iosynth+1);
2404 outb(regb, s->iosynth+2);
2405 outb(0, s->iosynth+3);
2406 }
2407 wake_up(&s->open_wait);
2408 up(&s->open_sem);
2409 unlock_kernel();
2410 return0;
2411 }
2412
2413 static/*const*/struct file_operations sv_dmfm_fops = {
2414  owner: THIS_MODULE,
2415  llseek: sv_llseek,
2416  ioctl: sv_dmfm_ioctl,
2417  open: sv_dmfm_open,
2418  release: sv_dmfm_release,
2419 };
2420
2421 /* --------------------------------------------------------------------- */
2422
2423 /* maximum number of devices; only used for command line params */
2424 #define NR_DEVICE 5
2425
2426 static int reverb[NR_DEVICE] = {0, };
2427
2428 #if 0
2429 static int wavetable[NR_DEVICE] = {0, };
2430 #endif
2431
2432 static unsigned int devindex =0;
2433
2434 MODULE_PARM(reverb,"1-"__MODULE_STRING(NR_DEVICE)"i");
2435 MODULE_PARM_DESC(reverb,"if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
2436 #if 0
2437 MODULE_PARM(wavetable,"1-"__MODULE_STRING(NR_DEVICE)"i");
2438 MODULE_PARM_DESC(wavetable,"if 1 the wavetable synth is enabled");
2439 #endif
2440
2441 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2442 MODULE_DESCRIPTION("S3 SonicVibes Driver");
2443
2444 /* --------------------------------------------------------------------- */
2445
2446 static struct initvol {
2447 int mixch;
2448 int vol;
2449 } initvol[] __initdata = {
2450 { SOUND_MIXER_WRITE_RECLEV,0x4040},
2451 { SOUND_MIXER_WRITE_LINE1,0x4040},
2452 { SOUND_MIXER_WRITE_CD,0x4040},
2453 { SOUND_MIXER_WRITE_LINE,0x4040},
2454 { SOUND_MIXER_WRITE_MIC,0x4040},
2455 { SOUND_MIXER_WRITE_SYNTH,0x4040},
2456 { SOUND_MIXER_WRITE_LINE2,0x4040},
2457 { SOUND_MIXER_WRITE_VOLUME,0x4040},
2458 { SOUND_MIXER_WRITE_PCM,0x4040}
2459 };
2460
2461 #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
2462  (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
2463
2464 static int __devinit sv_probe(struct pci_dev *pcidev,const struct pci_device_id *pciid)
2465 {
2466 static const char __initdata sv_ddma_name[] ="S3 Inc. SonicVibes DDMA Controller";
2467 struct sv_state *s;
2468  mm_segment_t fs;
2469 int i, val;
2470 char*ddmaname;
2471 unsigned ddmanamelen;
2472
2473 if(!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
2474 !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
2475 !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
2476 !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
2477 !RSRCISIOREGION(pcidev, RESOURCE_GAME))
2478 return-1;
2479 if(pcidev->irq ==0)
2480 return-1;
2481 if(!pci_dma_supported(pcidev,0x00ffffff)) {
2482 printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
2483 return-1;
2484 }
2485 /* try to allocate a DDMA resource if not already available */
2486 if(!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
2487  pcidev->resource[RESOURCE_DDMA].start =0;
2488  pcidev->resource[RESOURCE_DDMA].end =2*SV_EXTENT_DMA-1;
2489  pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
2490  ddmanamelen =strlen(sv_ddma_name)+1;
2491 if(!(ddmaname =kmalloc(ddmanamelen, GFP_KERNEL)))
2492 return-1;
2493 memcpy(ddmaname, sv_ddma_name, ddmanamelen);
2494  pcidev->resource[RESOURCE_DDMA].name = ddmaname;
2495 if(pci_assign_resource(pcidev, RESOURCE_DDMA)) {
2496  pcidev->resource[RESOURCE_DDMA].name = NULL;
2497 kfree(ddmaname);
2498 printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
2499 return-1;
2500 }
2501 }
2502 if(!(s =kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
2503 printk(KERN_WARNING "sv: out of memory\n");
2504 return-1;
2505 }
2506 memset(s,0,sizeof(struct sv_state));
2507 init_waitqueue_head(&s->dma_adc.wait);
2508 init_waitqueue_head(&s->dma_dac.wait);
2509 init_waitqueue_head(&s->open_wait);
2510 init_waitqueue_head(&s->midi.iwait);
2511 init_waitqueue_head(&s->midi.owait);
2512 init_MUTEX(&s->open_sem);
2513 spin_lock_init(&s->lock);
2514  s->magic = SV_MAGIC;
2515  s->dev = pcidev;
2516  s->iosb =pci_resource_start(pcidev, RESOURCE_SB);
2517  s->ioenh =pci_resource_start(pcidev, RESOURCE_ENH);
2518  s->iosynth =pci_resource_start(pcidev, RESOURCE_SYNTH);
2519  s->iomidi =pci_resource_start(pcidev, RESOURCE_MIDI);
2520  s->iogame =pci_resource_start(pcidev, RESOURCE_GAME);
2521  s->iodmaa =pci_resource_start(pcidev, RESOURCE_DDMA);
2522  s->iodmac =pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
2523 pci_write_config_dword(pcidev,0x40, s->iodmaa |9);/* enable and use extended mode */
2524 pci_write_config_dword(pcidev,0x48, s->iodmac |9);/* enable */
2525 printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#lx %#x %#x\n",
2526  s->iosb, s->ioenh, s->iosynth, s->iomidi, s->iogame, s->iodmaa, s->iodmac);
2527  s->irq = pcidev->irq;
2528
2529 /* hack */
2530 pci_write_config_dword(pcidev,0x60, wavetable_mem >>12);/* wavetable base address */
2531
2532 if(!request_region(s->ioenh, SV_EXTENT_ENH,"S3 SonicVibes PCM")) {
2533 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
2534 goto err_region5;
2535 }
2536 if(!request_region(s->iodmaa, SV_EXTENT_DMA,"S3 SonicVibes DMAA")) {
2537 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
2538 goto err_region4;
2539 }
2540 if(!request_region(s->iodmac, SV_EXTENT_DMA,"S3 SonicVibes DMAC")) {
2541 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
2542 goto err_region3;
2543 }
2544 if(!request_region(s->iomidi, SV_EXTENT_MIDI,"S3 SonicVibes Midi")) {
2545 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
2546 goto err_region2;
2547 }
2548 if(!request_region(s->iosynth, SV_EXTENT_SYNTH,"S3 SonicVibes Synth")) {
2549 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
2550 goto err_region1;
2551 }
2552 if(pci_enable_device(pcidev))
2553 goto err_irq;
2554 /* initialize codec registers */
2555 outb(0x80, s->ioenh + SV_CODEC_CONTROL);/* assert reset */
2556 udelay(50);
2557 outb(0x00, s->ioenh + SV_CODEC_CONTROL);/* deassert reset */
2558 udelay(50);
2559 outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
2560 | (reverb[devindex] ? SV_CCTRL_REVERB :0), s->ioenh + SV_CODEC_CONTROL);
2561 inb(s->ioenh + SV_CODEC_STATUS);/* clear ints */
2562 wrindir(s, SV_CIDRIVECONTROL,0);/* drive current 16mA */
2563 wrindir(s, SV_CIENABLE, s->enable =0);/* disable DMAA and DMAC */
2564 outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
2565 /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
2566 /* outb(0xff, s->iodmac + SV_DMA_RESET); */
2567 inb(s->ioenh + SV_CODEC_STATUS);/* ack interrupts */
2568 wrindir(s, SV_CIADCCLKSOURCE,0);/* use pll as ADC clock source */
2569 wrindir(s, SV_CIANALOGPWRDOWN,0);/* power up the analog parts of the device */
2570 wrindir(s, SV_CIDIGITALPWRDOWN,0);/* power up the digital parts of the device */
2571 setpll(s, SV_CIADCPLLM,8000);
2572 wrindir(s, SV_CISRSSPACE,0x80);/* SRS off */
2573 wrindir(s, SV_CIPCMSR0, (8000*65536/ FULLRATE) &0xff);
2574 wrindir(s, SV_CIPCMSR1, ((8000*65536/ FULLRATE) >>8) &0xff);
2575 wrindir(s, SV_CIADCOUTPUT,0);
2576 /* request irq */
2577 if(request_irq(s->irq, sv_interrupt, SA_SHIRQ,"S3 SonicVibes", s)) {
2578 printk(KERN_ERR "sv: irq %u in use\n", s->irq);
2579 goto err_irq;
2580 }
2581 printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
2582  s->ioenh, s->irq, s->iodmaa, s->iodmac,rdindir(s, SV_CIREVISION));
2583 /* register devices */
2584 if((s->dev_audio =register_sound_dsp(&sv_audio_fops, -1)) <0)
2585 goto err_dev1;
2586 if((s->dev_mixer =register_sound_mixer(&sv_mixer_fops, -1)) <0)
2587 goto err_dev2;
2588 if((s->dev_midi =register_sound_midi(&sv_midi_fops, -1)) <0)
2589 goto err_dev3;
2590 if((s->dev_dmfm =register_sound_special(&sv_dmfm_fops,15/* ?? */)) <0)
2591 goto err_dev4;
2592 pci_set_master(pcidev);/* enable bus mastering */
2593 /* initialize the chips */
2594  fs =get_fs();
2595 set_fs(KERNEL_DS);
2596  val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
2597 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2598 for(i =0; i <sizeof(initvol)/sizeof(initvol[0]); i++) {
2599  val = initvol[i].vol;
2600 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2601 }
2602 set_fs(fs);
2603 /* store it in the driver field */
2604 pci_set_drvdata(pcidev, s);
2605  pcidev->dma_mask =0x00ffffff;
2606 /* put it into driver list */
2607 list_add_tail(&s->devs, &devs);
2608 /* increment devindex */
2609 if(devindex < NR_DEVICE-1)
2610  devindex++;
2611 return0;
2612
2613  err_dev4:
2614 unregister_sound_midi(s->dev_midi);
2615  err_dev3:
2616 unregister_sound_mixer(s->dev_mixer);
2617  err_dev2:
2618 unregister_sound_dsp(s->dev_audio);
2619  err_dev1:
2620 printk(KERN_ERR "sv: cannot register misc device\n");
2621 free_irq(s->irq, s);
2622  err_irq:
2623 release_region(s->iosynth, SV_EXTENT_SYNTH);
2624  err_region1:
2625 release_region(s->iomidi, SV_EXTENT_MIDI);
2626  err_region2:
2627 release_region(s->iodmac, SV_EXTENT_DMA);
2628  err_region3:
2629 release_region(s->iodmaa, SV_EXTENT_DMA);
2630  err_region4:
2631 release_region(s->ioenh, SV_EXTENT_ENH);
2632  err_region5:
2633 kfree(s);
2634 return-1;
2635 }
2636
2637 static void __devinit sv_remove(struct pci_dev *dev)
2638 {
2639 struct sv_state *s =pci_get_drvdata(dev);
2640
2641 if(!s)
2642 return;
2643 list_del(&s->devs);
2644 outb(~0, s->ioenh + SV_CODEC_INTMASK);/* disable ints */
2645 synchronize_irq();
2646 inb(s->ioenh + SV_CODEC_STATUS);/* ack interrupts */
2647 wrindir(s, SV_CIENABLE,0);/* disable DMAA and DMAC */
2648 /*outb(0, s->iodmaa + SV_DMA_RESET);*/
2649 /*outb(0, s->iodmac + SV_DMA_RESET);*/
2650 free_irq(s->irq, s);
2651 release_region(s->iodmac, SV_EXTENT_DMA);
2652 release_region(s->iodmaa, SV_EXTENT_DMA);
2653 release_region(s->ioenh, SV_EXTENT_ENH);
2654 release_region(s->iomidi, SV_EXTENT_MIDI);
2655 release_region(s->iosynth, SV_EXTENT_SYNTH);
2656 unregister_sound_dsp(s->dev_audio);
2657 unregister_sound_mixer(s->dev_mixer);
2658 unregister_sound_midi(s->dev_midi);
2659 unregister_sound_special(s->dev_dmfm);
2660 kfree(s);
2661 pci_set_drvdata(dev, NULL);
2662 }
2663
2664 static struct pci_device_id id_table[] __devinitdata = {
2665 { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID,0,0},
2666 {0, }
2667 };
2668
2669 MODULE_DEVICE_TABLE(pci, id_table);
2670
2671 static struct pci_driver sv_driver = {
2672  name:"sonicvibes",
2673  id_table: id_table,
2674  probe: sv_probe,
2675  remove: sv_remove
2676 };
2677
2678 static int __init init_sonicvibes(void)
2679 {
2680 if(!pci_present())/* No PCI bus in this machine! */
2681 return-ENODEV;
2682 printk(KERN_INFO "sv: version v0.27 time " __TIME__ " " __DATE__ "\n");
2683 #if 0
2684 if(!(wavetable_mem =__get_free_pages(GFP_KERNEL,20-PAGE_SHIFT)))
2685 printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
2686 #endif
2687 returnpci_module_init(&sv_driver);
2688 }
2689
2690 static void __exit cleanup_sonicvibes(void)
2691 {
2692 printk(KERN_INFO "sv: unloading\n");
2693 pci_unregister_driver(&sv_driver);
2694 if(wavetable_mem)
2695 free_pages(wavetable_mem,20-PAGE_SHIFT);
2696 }
2697
2698 module_init(init_sonicvibes);
2699 module_exit(cleanup_sonicvibes);
2700
2701 /* --------------------------------------------------------------------- */
2702
2703 #ifndef MODULE
2704
2705 /* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
2706
2707 static int __init sonicvibes_setup(char*str)
2708 {
2709 static unsigned __initdata nr_dev =0;
2710
2711 if(nr_dev >= NR_DEVICE)
2712 return0;
2713 #if 0
2714 if(get_option(&str, &reverb[nr_dev]) ==2)
2715 (void)get_option(&str, &wavetable[nr_dev]);
2716 #else
2717 (void)get_option(&str, &reverb[nr_dev]);
2718 #endif
2719
2720  nr_dev++;
2721 return1;
2722 }
2723
2724 __setup("sonicvibes=", sonicvibes_setup);
2725
2726 #endif/* MODULE */