drivers/sound/esssolo1.c

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 1 /*****************************************************************************/
 2
 3 /*
 4  * esssolo1.c -- ESS Technology Solo1 (ES1946) audio driver.
 5  *
 6  * Copyright (C) 1998-2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
 7  *
 8  * This program is free software; you can redistribute it and/or modify
 9  * it under the terms of the GNU General Public License as published by
 10  * the Free Software Foundation; either version 2 of the License, or
 11  * (at your option) any later version.
 12  *
 13  * This program is distributed in the hope that it will be useful,
 14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 16  * GNU General Public License for more details.
 17  *
 18  * You should have received a copy of the GNU General Public License
 19  * along with this program; if not, write to the Free Software
 20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 21  *
 22  * Module command line parameters:
 23  * none so far
 24  *
 25  * Supported devices:
 26  * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
 27  * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
 28  * /dev/midi simple MIDI UART interface, no ioctl
 29  *
 30  * Revision history
 31  * 10.11.1998 0.1 Initial release (without any hardware)
 32  * 22.03.1999 0.2 cinfo.blocks should be reset after GETxPTR ioctl.
 33  * reported by Johan Maes <joma@telindus.be>
 34  * return EAGAIN instead of EBUSY when O_NONBLOCK
 35  * read/write cannot be executed
 36  * 07.04.1999 0.3 implemented the following ioctl's: SOUND_PCM_READ_RATE,
 37  * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
 38  * Alpha fixes reported by Peter Jones <pjones@redhat.com>
 39  * 15.06.1999 0.4 Fix bad allocation bug.
 40  * Thanks to Deti Fliegl <fliegl@in.tum.de>
 41  * 28.06.1999 0.5 Add pci_set_master
 42  * 12.08.1999 0.6 Fix MIDI UART crashing the driver
 43  * Changed mixer semantics from OSS documented
 44  * behaviour to OSS "code behaviour".
 45  * Recording might actually work now.
 46  * The real DDMA controller address register is at PCI config
 47  * 0x60, while the register at 0x18 is used as a placeholder
 48  * register for BIOS address allocation. This register
 49  * is supposed to be copied into 0x60, according
 50  * to the Solo1 datasheet. When I do that, I can access
 51  * the DDMA registers except the mask bit, which
 52  * is stuck at 1. When I copy the contents of 0x18 +0x10
 53  * to the DDMA base register, everything seems to work.
 54  * The fun part is that the Windows Solo1 driver doesn't
 55  * seem to do these tricks.
 56  * Bugs remaining: plops and clicks when starting/stopping playback
 57  * 31.08.1999 0.7 add spin_lock_init
 58  * replaced current->state = x with set_current_state(x)
 59  * 03.09.1999 0.8 change read semantics for MIDI to match
 60  * OSS more closely; remove possible wakeup race
 61  * 07.10.1999 0.9 Fix initialization; complain if sequencer writes time out
 62  * Revised resource grabbing for the FM synthesizer
 63  * 28.10.1999 0.10 More waitqueue races fixed
 64  * 09.12.1999 0.11 Work around stupid Alpha port issue (virt_to_bus(kmalloc(GFP_DMA)) > 16M)
 65  * Disabling recording on Alpha
 66  * 12.01.2000 0.12 Prevent some ioctl's from returning bad count values on underrun/overrun;
 67  * Tim Janik's BSE (Bedevilled Sound Engine) found this
 68  * Integrated (aka redid 8-)) APM support patch by Zach Brown
 69  * 07.02.2000 0.13 Use pci_alloc_consistent and pci_register_driver
 70  * 19.02.2000 0.14 Use pci_dma_supported to determine if recording should be disabled
 71  * 13.03.2000 0.15 Reintroduce initialization of a couple of PCI config space registers
 72  * 21.11.2000 0.16 Initialize dma buffers in poll, otherwise poll may return a bogus mask
 73  */
 74
 75 /*****************************************************************************/
 76
 77 #include <linux/version.h>
 78 #include <linux/module.h>
 79 #include <linux/string.h>
 80 #include <linux/ioport.h>
 81 #include <linux/sched.h>
 82 #include <linux/delay.h>
 83 #include <linux/sound.h>
 84 #include <linux/malloc.h>
 85 #include <linux/soundcard.h>
 86 #include <linux/pci.h>
 87 #include <linux/bitops.h>
 88 #include <linux/pm.h>
 89 #include <asm/io.h>
 90 #include <asm/dma.h>
 91 #include <linux/init.h>
 92 #include <linux/poll.h>
 93 #include <linux/spinlock.h>
 94 #include <linux/smp_lock.h>
 95 #include <linux/wrapper.h>
 96 #include <asm/uaccess.h>
 97 #include <asm/hardirq.h>
 98
 99 #include"dm.h"
 100
 101 /* --------------------------------------------------------------------- */
 102
 103 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
 104
 105 /* --------------------------------------------------------------------- */
 106
 107 #ifndef PCI_VENDOR_ID_ESS
 108 #define PCI_VENDOR_ID_ESS 0x125d
 109 #endif
 110 #ifndef PCI_DEVICE_ID_ESS_SOLO1
 111 #define PCI_DEVICE_ID_ESS_SOLO1 0x1969
 112 #endif
 113
 114 #define SOLO1_MAGIC ((PCI_VENDOR_ID_ESS<<16)|PCI_DEVICE_ID_ESS_SOLO1)
 115
 116 #define DDMABASE_OFFSET 0/* chip bug workaround kludge */
 117 #define DDMABASE_EXTENT 16
 118
 119 #define IOBASE_EXTENT 16
 120 #define SBBASE_EXTENT 16
 121 #define VCBASE_EXTENT (DDMABASE_EXTENT+DDMABASE_OFFSET)
 122 #define MPUBASE_EXTENT 4
 123 #define GPBASE_EXTENT 4
 124
 125 #define FMSYNTH_EXTENT 4
 126
 127 /* MIDI buffer sizes */
 128
 129 #define MIDIINBUF 256
 130 #define MIDIOUTBUF 256
 131
 132 #define FMODE_MIDI_SHIFT 3
 133 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
 134 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
 135
 136 #define FMODE_DMFM 0x10
 137
 138 /* --------------------------------------------------------------------- */
 139
 140 struct solo1_state {
 141 /* magic */
 142 unsigned int magic;
 143
 144 /* list of esssolo1 devices */
 145 struct list_head devs;
 146
 147 /* the corresponding pci_dev structure */
 148 struct pci_dev *dev;
 149
 150 /* soundcore stuff */
 151 int dev_audio;
 152 int dev_mixer;
 153 int dev_midi;
 154 int dev_dmfm;
 155
 156 /* hardware resources */
 157 unsigned long iobase, sbbase, vcbase, ddmabase, mpubase, gpbase;/* long for SPARC */
 158 unsigned int irq;
 159
 160 /* mixer registers */
 161 struct{
 162 unsigned short vol[10];
 163 unsigned int recsrc;
 164 unsigned int modcnt;
 165 unsigned short micpreamp;
 166 } mix;
 167
 168 /* wave stuff */
 169 unsigned fmt;
 170 unsigned channels;
 171 unsigned rate;
 172 unsigned char clkdiv;
 173 unsigned ena;
 174
 175  spinlock_t lock;
 176 struct semaphore open_sem;
 177  mode_t open_mode;
 178  wait_queue_head_t open_wait;
 179
 180 struct dmabuf {
 181 void*rawbuf;
 182  dma_addr_t dmaaddr;
 183 unsigned buforder;
 184 unsigned numfrag;
 185 unsigned fragshift;
 186 unsigned hwptr, swptr;
 187 unsigned total_bytes;
 188 int count;
 189 unsigned error;/* over/underrun */
 190  wait_queue_head_t wait;
 191 /* redundant, but makes calculations easier */
 192 unsigned fragsize;
 193 unsigned dmasize;
 194 unsigned fragsamples;
 195 /* OSS stuff */
 196 unsigned mapped:1;
 197 unsigned ready:1;
 198 unsigned endcleared:1;
 199 unsigned ossfragshift;
 200 int ossmaxfrags;
 201 unsigned subdivision;
 202 } dma_dac, dma_adc;
 203
 204 /* midi stuff */
 205 struct{
 206 unsigned ird, iwr, icnt;
 207 unsigned ord, owr, ocnt;
 208  wait_queue_head_t iwait;
 209  wait_queue_head_t owait;
 210 struct timer_list timer;
 211 unsigned char ibuf[MIDIINBUF];
 212 unsigned char obuf[MIDIOUTBUF];
 213 } midi;
 214 };
 215
 216 /* --------------------------------------------------------------------- */
 217
 218 staticLIST_HEAD(devs);
 219
 220 /* --------------------------------------------------------------------- */
 221
 222 extern inlinevoidwrite_seq(struct solo1_state *s,unsigned char data)
 223 {
 224 int i;
 225 unsigned long flags;
 226
 227 /* the __cli stunt is to send the data within the command window */
 228 for(i =0; i <0xffff; i++) {
 229 __save_flags(flags);
 230 __cli();
 231 if(!(inb(s->sbbase+0xc) &0x80)) {
 232 outb(data, s->sbbase+0xc);
 233 __restore_flags(flags);
 234 return;
 235 }
 236 __restore_flags(flags);
 237 }
 238 printk(KERN_ERR "esssolo1: write_seq timeout\n");
 239 outb(data, s->sbbase+0xc);
 240 }
 241
 242 extern inlineintread_seq(struct solo1_state *s,unsigned char*data)
 243 {
 244 int i;
 245
 246 if(!data)
 247 return0;
 248 for(i =0; i <0xffff; i++)
 249 if(inb(s->sbbase+0xe) &0x80) {
 250 *data =inb(s->sbbase+0xa);
 251 return1;
 252 }
 253 printk(KERN_ERR "esssolo1: read_seq timeout\n");
 254 return0;
 255 }
 256
 257 static intinlinereset_ctrl(struct solo1_state *s)
 258 {
 259 int i;
 260
 261 outb(3, s->sbbase+6);/* clear sequencer and FIFO */
 262 udelay(10);
 263 outb(0, s->sbbase+6);
 264 for(i =0; i <0xffff; i++)
 265 if(inb(s->sbbase+0xe) &0x80)
 266 if(inb(s->sbbase+0xa) ==0xaa) {
 267 write_seq(s,0xc6);/* enter enhanced mode */
 268 return1;
 269 }
 270 return0;
 271 }
 272
 273 static voidwrite_ctrl(struct solo1_state *s,unsigned char reg,unsigned char data)
 274 {
 275 write_seq(s, reg);
 276 write_seq(s, data);
 277 }
 278
 279 #if 0/* unused */
 280 static unsigned charread_ctrl(struct solo1_state *s,unsigned char reg)
 281 {
 282 unsigned char r;
 283
 284 write_seq(s,0xc0);
 285 write_seq(s, reg);
 286 read_seq(s, &r);
 287 return r;
 288 }
 289 #endif/* unused */
 290
 291 static voidwrite_mixer(struct solo1_state *s,unsigned char reg,unsigned char data)
 292 {
 293 outb(reg, s->sbbase+4);
 294 outb(data, s->sbbase+5);
 295 }
 296
 297 static unsigned charread_mixer(struct solo1_state *s,unsigned char reg)
 298 {
 299 outb(reg, s->sbbase+4);
 300 returninb(s->sbbase+5);
 301 }
 302
 303 /* --------------------------------------------------------------------- */
 304
 305 extern inlineunsignedld2(unsigned int x)
 306 {
 307 unsigned r =0;
 308
 309 if(x >=0x10000) {
 310  x >>=16;
 311  r +=16;
 312 }
 313 if(x >=0x100) {
 314  x >>=8;
 315  r +=8;
 316 }
 317 if(x >=0x10) {
 318  x >>=4;
 319  r +=4;
 320 }
 321 if(x >=4) {
 322  x >>=2;
 323  r +=2;
 324 }
 325 if(x >=2)
 326  r++;
 327 return r;
 328 }
 329
 330 /* --------------------------------------------------------------------- */
 331
 332 extern inlinevoidstop_dac(struct solo1_state *s)
 333 {
 334 unsigned long flags;
 335
 336 spin_lock_irqsave(&s->lock, flags);
 337  s->ena &= ~FMODE_WRITE;
 338 write_mixer(s,0x78,0x10);
 339 spin_unlock_irqrestore(&s->lock, flags);
 340 }
 341
 342 static voidstart_dac(struct solo1_state *s)
 343 {
 344 unsigned long flags;
 345
 346 spin_lock_irqsave(&s->lock, flags);
 347 if(!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || s->dma_dac.count >0) && s->dma_dac.ready) {
 348  s->ena |= FMODE_WRITE;
 349 write_mixer(s,0x78,0x12);
 350 udelay(10);
 351 write_mixer(s,0x78,0x13);
 352 }
 353 spin_unlock_irqrestore(&s->lock, flags);
 354 }
 355
 356 extern inlinevoidstop_adc(struct solo1_state *s)
 357 {
 358 unsigned long flags;
 359
 360 spin_lock_irqsave(&s->lock, flags);
 361  s->ena &= ~FMODE_READ;
 362 write_ctrl(s,0xb8,0xe);
 363 spin_unlock_irqrestore(&s->lock, flags);
 364 }
 365
 366 static voidstart_adc(struct solo1_state *s)
 367 {
 368 unsigned long flags;
 369
 370 spin_lock_irqsave(&s->lock, flags);
 371 if(!(s->ena & FMODE_READ) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize -2*s->dma_adc.fragsize))
 372 && s->dma_adc.ready) {
 373  s->ena |= FMODE_READ;
 374 write_ctrl(s,0xb8,0xf);
 375 #if 0
 376 printk(KERN_DEBUG "solo1: DMAbuffer: 0x%08lx\n", (long)s->dma_adc.rawbuf);
 377 printk(KERN_DEBUG "solo1: DMA: mask: 0x%02x cnt: 0x%04x addr: 0x%08x stat: 0x%02x\n",
 378 inb(s->ddmabase+0xf),inw(s->ddmabase+4),inl(s->ddmabase),inb(s->ddmabase+8));
 379 #endif
 380 outb(0, s->ddmabase+0xd);/* master reset */
 381 outb(1, s->ddmabase+0xf);/* mask */
 382 outb(0x54/*0x14*/, s->ddmabase+0xb);/* DMA_MODE_READ | DMA_MODE_AUTOINIT */
 383 outl(virt_to_bus(s->dma_adc.rawbuf), s->ddmabase);
 384 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
 385 outb(0, s->ddmabase+0xf);
 386 }
 387 spin_unlock_irqrestore(&s->lock, flags);
 388 #if 0
 389 printk(KERN_DEBUG "solo1: start DMA: reg B8: 0x%02x SBstat: 0x%02x\n"
 390  KERN_DEBUG "solo1: DMA: stat: 0x%02x cnt: 0x%04x mask: 0x%02x\n",
 391 read_ctrl(s,0xb8),inb(s->sbbase+0xc),
 392 inb(s->ddmabase+8),inw(s->ddmabase+4),inb(s->ddmabase+0xf));
 393 printk(KERN_DEBUG "solo1: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
 394  KERN_DEBUG "solo1: B1: 0x%02x B2: 0x%02x B4: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n",
 395 read_ctrl(s,0xa1),read_ctrl(s,0xa2),read_ctrl(s,0xa4),read_ctrl(s,0xa5),read_ctrl(s,0xa8),
 396 read_ctrl(s,0xb1),read_ctrl(s,0xb2),read_ctrl(s,0xb4),read_ctrl(s,0xb7),read_ctrl(s,0xb8),
 397 read_ctrl(s,0xb9));
 398 #endif
 399 }
 400
 401 /* --------------------------------------------------------------------- */
 402
 403 #define DMABUF_DEFAULTORDER (15-PAGE_SHIFT)
 404 #define DMABUF_MINORDER 1
 405
 406 extern inlinevoiddealloc_dmabuf(struct solo1_state *s,struct dmabuf *db)
 407 {
 408 struct page *page, *pend;
 409
 410 if(db->rawbuf) {
 411 /* undo marking the pages as reserved */
 412  pend =virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -1);
 413 for(page =virt_to_page(db->rawbuf); page <= pend; page++)
 414 mem_map_unreserve(page);
 415 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
 416 }
 417  db->rawbuf = NULL;
 418  db->mapped = db->ready =0;
 419 }
 420
 421 static intprog_dmabuf(struct solo1_state *s,struct dmabuf *db)
 422 {
 423 int order;
 424 unsigned bytespersec;
 425 unsigned bufs, sample_shift =0;
 426 struct page *page, *pend;
 427
 428  db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared =0;
 429 if(!db->rawbuf) {
 430  db->ready = db->mapped =0;
 431 for(order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
 432 if((db->rawbuf =pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
 433 break;
 434 if(!db->rawbuf)
 435 return-ENOMEM;
 436  db->buforder = order;
 437 /* now mark the pages as reserved; otherwise remap_page_range doesn't do what we want */
 438  pend =virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) -1);
 439 for(page =virt_to_page(db->rawbuf); page <= pend; page++)
 440 mem_map_reserve(page);
 441 }
 442 if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
 443  sample_shift++;
 444 if(s->channels >1)
 445  sample_shift++;
 446  bytespersec = s->rate << sample_shift;
 447  bufs = PAGE_SIZE << db->buforder;
 448 if(db->ossfragshift) {
 449 if((1000<< db->ossfragshift) < bytespersec)
 450  db->fragshift =ld2(bytespersec/1000);
 451 else
 452  db->fragshift = db->ossfragshift;
 453 }else{
 454  db->fragshift =ld2(bytespersec/100/(db->subdivision ? db->subdivision :1));
 455 if(db->fragshift <3)
 456  db->fragshift =3;
 457 }
 458  db->numfrag = bufs >> db->fragshift;
 459 while(db->numfrag <4&& db->fragshift >3) {
 460  db->fragshift--;
 461  db->numfrag = bufs >> db->fragshift;
 462 }
 463  db->fragsize =1<< db->fragshift;
 464 if(db->ossmaxfrags >=4&& db->ossmaxfrags < db->numfrag)
 465  db->numfrag = db->ossmaxfrags;
 466  db->fragsamples = db->fragsize >> sample_shift;
 467  db->dmasize = db->numfrag << db->fragshift;
 468 return0;
 469 }
 470
 471 extern inlineintprog_dmabuf_adc(struct solo1_state *s)
 472 {
 473 unsigned long va;
 474 int c;
 475
 476 stop_adc(s);
 477 /* check if PCI implementation supports 24bit busmaster DMA */
 478 if(s->dev->dma_mask >0xffffff)
 479 return-EIO;
 480 if((c =prog_dmabuf(s, &s->dma_adc)))
 481 return c;
 482  va = s->dma_adc.dmaaddr;
 483 if((va & ~((1<<24)-1)))
 484 panic("solo1: buffer above 16M boundary");
 485 outb(0, s->ddmabase+0xd);/* clear */
 486 outb(1, s->ddmabase+0xf);/* mask */
 487 /*outb(0, s->ddmabase+8);*//* enable (enable is active low!) */
 488 outb(0x54, s->ddmabase+0xb);/* DMA_MODE_READ | DMA_MODE_AUTOINIT */
 489 outl(va, s->ddmabase);
 490 outw(s->dma_adc.dmasize-1, s->ddmabase+4);
 491  c = - s->dma_adc.fragsamples;
 492 write_ctrl(s,0xa4, c);
 493 write_ctrl(s,0xa5, c >>8);
 494 outb(0, s->ddmabase+0xf);
 495  s->dma_adc.ready =1;
 496 return0;
 497 }
 498
 499 extern inlineintprog_dmabuf_dac(struct solo1_state *s)
 500 {
 501 unsigned long va;
 502 int c;
 503
 504 stop_dac(s);
 505 if((c =prog_dmabuf(s, &s->dma_dac)))
 506 return c;
 507 memset(s->dma_dac.rawbuf, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ?0:0x80, s->dma_dac.dmasize);/* almost correct for U16 */
 508  va = s->dma_dac.dmaaddr;
 509 if((va ^ (va + s->dma_dac.dmasize -1)) & ~((1<<20)-1))
 510 panic("solo1: buffer crosses 1M boundary");
 511 outl(va, s->iobase);
 512 /* warning: s->dma_dac.dmasize & 0xffff must not be zero! i.e. this limits us to a 32k buffer */
 513 outw(s->dma_dac.dmasize, s->iobase+4);
 514  c = - s->dma_dac.fragsamples;
 515 write_mixer(s,0x74, c);
 516 write_mixer(s,0x76, c >>8);
 517 outb(0xa, s->iobase+6);
 518  s->dma_dac.ready =1;
 519 return0;
 520 }
 521
 522 extern inlinevoidclear_advance(void*buf,unsigned bsize,unsigned bptr,unsigned len,unsigned char c)
 523 {
 524 if(bptr + len > bsize) {
 525 unsigned x = bsize - bptr;
 526 memset(((char*)buf) + bptr, c, x);
 527  bptr =0;
 528  len -= x;
 529 }
 530 memset(((char*)buf) + bptr, c, len);
 531 }
 532
 533 /* call with spinlock held! */
 534
 535 static voidsolo1_update_ptr(struct solo1_state *s)
 536 {
 537 int diff;
 538 unsigned hwptr;
 539
 540 /* update ADC pointer */
 541 if(s->ena & FMODE_READ) {
 542  hwptr = (s->dma_adc.dmasize -1-inw(s->ddmabase+4)) % s->dma_adc.dmasize;
 543  diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
 544  s->dma_adc.hwptr = hwptr;
 545  s->dma_adc.total_bytes += diff;
 546  s->dma_adc.count += diff;
 547 #if 0
 548 printk(KERN_DEBUG "solo1: rd: hwptr %u swptr %u dmasize %u count %u\n",
 549  s->dma_adc.hwptr, s->dma_adc.swptr, s->dma_adc.dmasize, s->dma_adc.count);
 550 #endif
 551 if(s->dma_adc.mapped) {
 552 if(s->dma_adc.count >= (signed)s->dma_adc.fragsize)
 553 wake_up(&s->dma_adc.wait);
 554 }else{
 555 if(s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3* s->dma_adc.fragsize) >>1))) {
 556  s->ena &= ~FMODE_READ;
 557 write_ctrl(s,0xb8,0xe);
 558  s->dma_adc.error++;
 559 }
 560 if(s->dma_adc.count >0)
 561 wake_up(&s->dma_adc.wait);
 562 }
 563 }
 564 /* update DAC pointer */
 565 if(s->ena & FMODE_WRITE) {
 566  hwptr = (s->dma_dac.dmasize -inw(s->iobase+4)) % s->dma_dac.dmasize;
 567  diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
 568  s->dma_dac.hwptr = hwptr;
 569  s->dma_dac.total_bytes += diff;
 570 #if 0
 571 printk(KERN_DEBUG "solo1: wr: hwptr %u swptr %u dmasize %u count %u\n",
 572  s->dma_dac.hwptr, s->dma_dac.swptr, s->dma_dac.dmasize, s->dma_dac.count);
 573 #endif
 574 if(s->dma_dac.mapped) {
 575  s->dma_dac.count += diff;
 576 if(s->dma_dac.count >= (signed)s->dma_dac.fragsize)
 577 wake_up(&s->dma_dac.wait);
 578 }else{
 579  s->dma_dac.count -= diff;
 580 if(s->dma_dac.count <=0) {
 581  s->ena &= ~FMODE_WRITE;
 582 write_mixer(s,0x78,0x12);
 583  s->dma_dac.error++;
 584 }else if(s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
 585 clear_advance(s->dma_dac.rawbuf, s->dma_dac.dmasize, s->dma_dac.swptr,
 586  s->dma_dac.fragsize, (s->fmt & (AFMT_U8 | AFMT_U16_LE)) ?0:0x80);
 587  s->dma_dac.endcleared =1;
 588 }
 589 if(s->dma_dac.count < (signed)s->dma_dac.dmasize)
 590 wake_up(&s->dma_dac.wait);
 591 }
 592 }
 593 }
 594
 595 /* --------------------------------------------------------------------- */
 596
 597 static voidprog_codec(struct solo1_state *s)
 598 {
 599 unsigned long flags;
 600 int fdiv, filter;
 601 unsigned char c;
 602
 603 reset_ctrl(s);
 604 write_seq(s,0xd3);
 605 /* program sampling rates */
 606  filter = s->rate *9/20;/* Set filter roll-off to 90% of rate/2 */
 607  fdiv =256-7160000/ (filter *82);
 608 spin_lock_irqsave(&s->lock, flags);
 609 write_ctrl(s,0xa1, s->clkdiv);
 610 write_ctrl(s,0xa2, fdiv);
 611 write_mixer(s,0x70, s->clkdiv);
 612 write_mixer(s,0x72, fdiv);
 613 /* program ADC parameters */
 614 write_ctrl(s,0xb8,0xe);
 615 write_ctrl(s,0xb9,/*0x1*/0);
 616 write_ctrl(s,0xa8, (s->channels >1) ?0x11:0x12);
 617  c =0xd0;
 618 if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
 619  c |=0x04;
 620 if(s->fmt & (AFMT_S16_LE | AFMT_S8))
 621  c |=0x20;
 622 if(s->channels >1)
 623  c ^=0x48;
 624 write_ctrl(s,0xb7, (c &0x70) |1);
 625 write_ctrl(s,0xb7, c);
 626 write_ctrl(s,0xb1,0x50);
 627 write_ctrl(s,0xb2,0x50);
 628 /* program DAC parameters */
 629  c =0x40;
 630 if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
 631  c |=1;
 632 if(s->fmt & (AFMT_S16_LE | AFMT_S8))
 633  c |=4;
 634 if(s->channels >1)
 635  c |=2;
 636 write_mixer(s,0x7a, c);
 637 write_mixer(s,0x78,0x10);
 638  s->ena =0;
 639 spin_unlock_irqrestore(&s->lock, flags);
 640 }
 641
 642 /* --------------------------------------------------------------------- */
 643
 644 static const char invalid_magic[] = KERN_CRIT "solo1: invalid magic value\n";
 645
 646 #define VALIDATE_STATE(s) \
 647 ({ \
 648  if (!(s) || (s)->magic != SOLO1_MAGIC) { \
 649  printk(invalid_magic); \
 650  return -ENXIO; \
 651  } \
 652 })
 653
 654 /* --------------------------------------------------------------------- */
 655
 656 static intmixer_ioctl(struct solo1_state *s,unsigned int cmd,unsigned long arg)
 657 {
 658 static const unsigned int mixer_src[8] = {
 659  SOUND_MASK_MIC, SOUND_MASK_MIC, SOUND_MASK_CD, SOUND_MASK_VOLUME,
 660  SOUND_MASK_MIC,0, SOUND_MASK_LINE,0
 661 };
 662 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 663 [SOUND_MIXER_PCM] =1,/* voice */
 664 [SOUND_MIXER_SYNTH] =2,/* FM */
 665 [SOUND_MIXER_CD] =3,/* CD */
 666 [SOUND_MIXER_LINE] =4,/* Line */
 667 [SOUND_MIXER_LINE1] =5,/* AUX */
 668 [SOUND_MIXER_MIC] =6,/* Mic */
 669 [SOUND_MIXER_LINE2] =7,/* Mono in */
 670 [SOUND_MIXER_SPEAKER] =8,/* Speaker */
 671 [SOUND_MIXER_RECLEV] =9,/* Recording level */
 672 [SOUND_MIXER_VOLUME] =10/* Master Volume */
 673 };
 674 static const unsigned char mixreg[] = {
 675 0x7c,/* voice */
 676 0x36,/* FM */
 677 0x38,/* CD */
 678 0x3e,/* Line */
 679 0x3a,/* AUX */
 680 0x1a,/* Mic */
 681 0x6d/* Mono in */
 682 };
 683 unsigned char l, r, rl, rr, vidx;
 684 int i, val;
 685
 686 VALIDATE_STATE(s);
 687
 688 if(cmd == SOUND_MIXER_PRIVATE1) {
 689 /* enable/disable/query mixer preamp */
 690 if(get_user(val, (int*)arg))
 691 return-EFAULT;
 692 if(val != -1) {
 693  val = val ?0xff:0xf7;
 694 write_mixer(s,0x7d, (read_mixer(s,0x7d) |0x08) & val);
 695 }
 696  val = (read_mixer(s,0x7d) &0x08) ?1:0;
 697 returnput_user(val, (int*)arg);
 698 }
 699 if(cmd == SOUND_MIXER_PRIVATE2) {
 700 /* enable/disable/query spatializer */
 701 if(get_user(val, (int*)arg))
 702 return-EFAULT;
 703 if(val != -1) {
 704  val &=0x3f;
 705 write_mixer(s,0x52, val);
 706 write_mixer(s,0x50, val ?0x08:0);
 707 }
 708 returnput_user(read_mixer(s,0x52), (int*)arg);
 709 }
 710 if(cmd == SOUND_MIXER_INFO) {
 711  mixer_info info;
 712 strncpy(info.id,"Solo1",sizeof(info.id));
 713 strncpy(info.name,"ESS Solo1",sizeof(info.name));
 714  info.modify_counter = s->mix.modcnt;
 715 if(copy_to_user((void*)arg, &info,sizeof(info)))
 716 return-EFAULT;
 717 return0;
 718 }
 719 if(cmd == SOUND_OLD_MIXER_INFO) {
 720  _old_mixer_info info;
 721 strncpy(info.id,"Solo1",sizeof(info.id));
 722 strncpy(info.name,"ESS Solo1",sizeof(info.name));
 723 if(copy_to_user((void*)arg, &info,sizeof(info)))
 724 return-EFAULT;
 725 return0;
 726 }
 727 if(cmd == OSS_GETVERSION)
 728 returnput_user(SOUND_VERSION, (int*)arg);
 729 if(_IOC_TYPE(cmd) !='M'||_SIOC_SIZE(cmd) !=sizeof(int))
 730 return-EINVAL;
 731 if(_SIOC_DIR(cmd) == _SIOC_READ) {
 732 switch(_IOC_NR(cmd)) {
 733 case SOUND_MIXER_RECSRC:/* Arg contains a bit for each recording source */
 734 returnput_user(mixer_src[read_mixer(s,0x1c) &7], (int*)arg);
 735
 736 case SOUND_MIXER_DEVMASK:/* Arg contains a bit for each supported device */
 737 returnput_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
 738  SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
 739  SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV |
 740  SOUND_MASK_SPEAKER, (int*)arg);
 741
 742 case SOUND_MIXER_RECMASK:/* Arg contains a bit for each supported recording source */
 743 returnput_user(SOUND_MASK_LINE | SOUND_MASK_MIC | SOUND_MASK_CD | SOUND_MASK_VOLUME, (int*)arg);
 744
 745 case SOUND_MIXER_STEREODEVS:/* Mixer channels supporting stereo */
 746 returnput_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH | SOUND_MASK_CD |
 747  SOUND_MASK_LINE | SOUND_MASK_LINE1 | SOUND_MASK_MIC |
 748  SOUND_MASK_VOLUME | SOUND_MASK_LINE2 | SOUND_MASK_RECLEV, (int*)arg);
 749
 750 case SOUND_MIXER_CAPS:
 751 returnput_user(SOUND_CAP_EXCL_INPUT, (int*)arg);
 752
 753 default:
 754  i =_IOC_NR(cmd);
 755 if(i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
 756 return-EINVAL;
 757 returnput_user(s->mix.vol[vidx-1], (int*)arg);
 758 }
 759 }
 760 if(_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
 761 return-EINVAL;
 762  s->mix.modcnt++;
 763 switch(_IOC_NR(cmd)) {
 764 case SOUND_MIXER_RECSRC:/* Arg contains a bit for each recording source */
 765 #if 0
 766 {
 767 static const unsigned char regs[] = {
 768 0x1c,0x1a,0x36,0x38,0x3a,0x3c,0x3e,0x60,0x62,0x6d,0x7c
 769 };
 770 int i;
 771
 772 for(i =0; i <sizeof(regs); i++)
 773 printk(KERN_DEBUG "solo1: mixer reg 0x%02x: 0x%02x\n",
 774  regs[i],read_mixer(s, regs[i]));
 775 printk(KERN_DEBUG "solo1: ctrl reg 0x%02x: 0x%02x\n",
 776 0xb4,read_ctrl(s,0xb4));
 777 }
 778 #endif
 779 if(get_user(val, (int*)arg))
 780 return-EFAULT;
 781  i =hweight32(val);
 782 if(i ==0)
 783 return0;
 784 else if(i >1)
 785  val &= ~mixer_src[read_mixer(s,0x1c) &7];
 786 for(i =0; i <8; i++) {
 787 if(mixer_src[i] & val)
 788 break;
 789 }
 790 if(i >7)
 791 return0;
 792 write_mixer(s,0x1c, i);
 793 return0;
 794
 795 case SOUND_MIXER_VOLUME:
 796 if(get_user(val, (int*)arg))
 797 return-EFAULT;
 798  l = val &0xff;
 799 if(l >100)
 800  l =100;
 801  r = (val >>8) &0xff;
 802 if(r >100)
 803  r =100;
 804 if(l <6) {
 805  rl =0x40;
 806  l =0;
 807 }else{
 808  rl = (l *2-11) /3;
 809  l = (rl *3+11) /2;
 810 }
 811 if(r <6) {
 812  rr =0x40;
 813  r =0;
 814 }else{
 815  rr = (r *2-11) /3;
 816  r = (rr *3+11) /2;
 817 }
 818 write_mixer(s,0x60, rl);
 819 write_mixer(s,0x62, rr);
 820 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
 821  s->mix.vol[9] = ((unsigned int)r <<8) | l;
 822 #else
 823  s->mix.vol[9] = val;
 824 #endif
 825 returnput_user(s->mix.vol[9], (int*)arg);
 826
 827 case SOUND_MIXER_SPEAKER:
 828 if(get_user(val, (int*)arg))
 829 return-EFAULT;
 830  l = val &0xff;
 831 if(l >100)
 832  l =100;
 833 else if(l <2)
 834  l =2;
 835  rl = (l -2) /14;
 836  l = rl *14+2;
 837 write_mixer(s,0x3c, rl);
 838 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
 839  s->mix.vol[7] = l *0x101;
 840 #else
 841  s->mix.vol[7] = val;
 842 #endif
 843 returnput_user(s->mix.vol[7], (int*)arg);
 844
 845 case SOUND_MIXER_RECLEV:
 846 if(get_user(val, (int*)arg))
 847 return-EFAULT;
 848  l = (val <<1) &0x1fe;
 849 if(l >200)
 850  l =200;
 851 else if(l <5)
 852  l =5;
 853  r = (val >>7) &0x1fe;
 854 if(r >200)
 855  r =200;
 856 else if(r <5)
 857  r =5;
 858  rl = (l -5) /13;
 859  rr = (r -5) /13;
 860  r = (rl *13+5) /2;
 861  l = (rr *13+5) /2;
 862 write_ctrl(s,0xb4, (rl <<4) | rr);
 863 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
 864  s->mix.vol[8] = ((unsigned int)r <<8) | l;
 865 #else
 866  s->mix.vol[8] = val;
 867 #endif
 868 returnput_user(s->mix.vol[8], (int*)arg);
 869
 870 default:
 871  i =_IOC_NR(cmd);
 872 if(i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
 873 return-EINVAL;
 874 if(get_user(val, (int*)arg))
 875 return-EFAULT;
 876  l = (val <<1) &0x1fe;
 877 if(l >200)
 878  l =200;
 879 else if(l <5)
 880  l =5;
 881  r = (val >>7) &0x1fe;
 882 if(r >200)
 883  r =200;
 884 else if(r <5)
 885  r =5;
 886  rl = (l -5) /13;
 887  rr = (r -5) /13;
 888  r = (rl *13+5) /2;
 889  l = (rr *13+5) /2;
 890 write_mixer(s, mixreg[vidx-1], (rl <<4) | rr);
 891 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
 892  s->mix.vol[vidx-1] = ((unsigned int)r <<8) | l;
 893 #else
 894  s->mix.vol[vidx-1] = val;
 895 #endif
 896 returnput_user(s->mix.vol[vidx-1], (int*)arg);
 897 }
 898 }
 899
 900 /* --------------------------------------------------------------------- */
 901
 902 static loff_t solo1_llseek(struct file *file, loff_t offset,int origin)
 903 {
 904 return-ESPIPE;
 905 }
 906
 907 /* --------------------------------------------------------------------- */
 908
 909 static intsolo1_open_mixdev(struct inode *inode,struct file *file)
 910 {
 911 int minor =MINOR(inode->i_rdev);
 912 struct list_head *list;
 913 struct solo1_state *s;
 914
 915 for(list = devs.next; ; list = list->next) {
 916 if(list == &devs)
 917 return-ENODEV;
 918  s =list_entry(list,struct solo1_state, devs);
 919 if(s->dev_mixer == minor)
 920 break;
 921 }
 922 VALIDATE_STATE(s);
 923  file->private_data = s;
 924 return0;
 925 }
 926
 927 static intsolo1_release_mixdev(struct inode *inode,struct file *file)
 928 {
 929 struct solo1_state *s = (struct solo1_state *)file->private_data;
 930
 931 VALIDATE_STATE(s);
 932 return0;
 933 }
 934
 935 static intsolo1_ioctl_mixdev(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
 936 {
 937 returnmixer_ioctl((struct solo1_state *)file->private_data, cmd, arg);
 938 }
 939
 940 static/*const*/struct file_operations solo1_mixer_fops = {
 941  owner: THIS_MODULE,
 942  llseek: solo1_llseek,
 943  ioctl: solo1_ioctl_mixdev,
 944  open: solo1_open_mixdev,
 945  release: solo1_release_mixdev,
 946 };
 947
 948 /* --------------------------------------------------------------------- */
 949
 950 static intdrain_dac(struct solo1_state *s,int nonblock)
 951 {
 952 DECLARE_WAITQUEUE(wait, current);
 953 unsigned long flags;
 954 int count;
 955 unsigned tmo;
 956
 957 if(s->dma_dac.mapped)
 958 return0;
 959 add_wait_queue(&s->dma_dac.wait, &wait);
 960 for(;;) {
 961 set_current_state(TASK_INTERRUPTIBLE);
 962 spin_lock_irqsave(&s->lock, flags);
 963  count = s->dma_dac.count;
 964 spin_unlock_irqrestore(&s->lock, flags);
 965 if(count <=0)
 966 break;
 967 if(signal_pending(current))
 968 break;
 969 if(nonblock) {
 970 remove_wait_queue(&s->dma_dac.wait, &wait);
 971 set_current_state(TASK_RUNNING);
 972 return-EBUSY;
 973 }
 974  tmo =3* HZ * (count + s->dma_dac.fragsize) /2/ s->rate;
 975 if(s->fmt & (AFMT_S16_LE | AFMT_U16_LE))
 976  tmo >>=1;
 977 if(s->channels >1)
 978  tmo >>=1;
 979 if(!schedule_timeout(tmo +1))
 980 printk(KERN_DEBUG "solo1: dma timed out??\n");
 981 }
 982 remove_wait_queue(&s->dma_dac.wait, &wait);
 983 set_current_state(TASK_RUNNING);
 984 if(signal_pending(current))
 985 return-ERESTARTSYS;
 986 return0;
 987 }
 988
 989 /* --------------------------------------------------------------------- */
 990
 991 static ssize_t solo1_read(struct file *file,char*buffer,size_t count, loff_t *ppos)
 992 {
 993 struct solo1_state *s = (struct solo1_state *)file->private_data;
 994 DECLARE_WAITQUEUE(wait, current);
 995  ssize_t ret;
 996 unsigned long flags;
 997 unsigned swptr;
 998 int cnt;
 999
1000 VALIDATE_STATE(s);
1001 if(ppos != &file->f_pos)
1002 return-ESPIPE;
1003 if(s->dma_adc.mapped)
1004 return-ENXIO;
1005 if(!s->dma_adc.ready && (ret =prog_dmabuf_adc(s)))
1006 return ret;
1007 if(!access_ok(VERIFY_WRITE, buffer, count))
1008 return-EFAULT;
1009  ret =0;
1010 add_wait_queue(&s->dma_adc.wait, &wait);
1011 while(count >0) {
1012 spin_lock_irqsave(&s->lock, flags);
1013  swptr = s->dma_adc.swptr;
1014  cnt = s->dma_adc.dmasize-swptr;
1015 if(s->dma_adc.count < cnt)
1016  cnt = s->dma_adc.count;
1017 if(cnt <=0)
1018 __set_current_state(TASK_INTERRUPTIBLE);
1019 spin_unlock_irqrestore(&s->lock, flags);
1020 if(cnt > count)
1021  cnt = count;
1022 #ifdef DEBUGREC
1023 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x cnt: %u\n",
1024 read_ctrl(s,0xb8),inb(s->ddmabase+8),inw(s->ddmabase+4),inb(s->sbbase+0xc), cnt);
1025 #endif
1026 if(cnt <=0) {
1027 start_adc(s);
1028 #ifdef DEBUGREC
1029 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1030  KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1031  KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1032  KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1033 read_ctrl(s,0xa1),read_ctrl(s,0xa2),read_ctrl(s,0xa4),read_ctrl(s,0xa5),read_ctrl(s,0xa8),
1034 read_ctrl(s,0xb1),read_ctrl(s,0xb2),read_ctrl(s,0xb7),read_ctrl(s,0xb8),read_ctrl(s,0xb9),
1035 inl(s->ddmabase),inw(s->ddmabase+4),inb(s->ddmabase+8),inb(s->ddmabase+15),inb(s->sbbase+0xc), cnt);
1036 #endif
1037 if(inb(s->ddmabase+15) &1)
1038 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1039 if(file->f_flags & O_NONBLOCK) {
1040 if(!ret)
1041  ret = -EAGAIN;
1042 break;
1043 }
1044 schedule();
1045 #ifdef DEBUGREC
1046 printk(KERN_DEBUG "solo1_read: regs: A1: 0x%02x A2: 0x%02x A4: 0x%02x A5: 0x%02x A8: 0x%02x\n"
1047  KERN_DEBUG "solo1_read: regs: B1: 0x%02x B2: 0x%02x B7: 0x%02x B8: 0x%02x B9: 0x%02x\n"
1048  KERN_DEBUG "solo1_read: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x mask: 0x%02x\n"
1049  KERN_DEBUG "solo1_read: SBstat: 0x%02x cnt: %u\n",
1050 read_ctrl(s,0xa1),read_ctrl(s,0xa2),read_ctrl(s,0xa4),read_ctrl(s,0xa5),read_ctrl(s,0xa8),
1051 read_ctrl(s,0xb1),read_ctrl(s,0xb2),read_ctrl(s,0xb7),read_ctrl(s,0xb8),read_ctrl(s,0xb9),
1052 inl(s->ddmabase),inw(s->ddmabase+4),inb(s->ddmabase+8),inb(s->ddmabase+15),inb(s->sbbase+0xc), cnt);
1053 #endif
1054 if(signal_pending(current)) {
1055 if(!ret)
1056  ret = -ERESTARTSYS;
1057 break;
1058 }
1059 continue;
1060 }
1061 if(copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1062 if(!ret)
1063  ret = -EFAULT;
1064 break;
1065 }
1066  swptr = (swptr + cnt) % s->dma_adc.dmasize;
1067 spin_lock_irqsave(&s->lock, flags);
1068  s->dma_adc.swptr = swptr;
1069  s->dma_adc.count -= cnt;
1070 spin_unlock_irqrestore(&s->lock, flags);
1071  count -= cnt;
1072  buffer += cnt;
1073  ret += cnt;
1074 start_adc(s);
1075 #ifdef DEBUGREC
1076 printk(KERN_DEBUG "solo1_read: reg B8: 0x%02x DMAstat: 0x%02x DMAcnt: 0x%04x SBstat: 0x%02x\n",
1077 read_ctrl(s,0xb8),inb(s->ddmabase+8),inw(s->ddmabase+4),inb(s->sbbase+0xc));
1078 #endif
1079 }
1080 remove_wait_queue(&s->dma_adc.wait, &wait);
1081 set_current_state(TASK_RUNNING);
1082 return ret;
1083 }
1084
1085 static ssize_t solo1_write(struct file *file,const char*buffer,size_t count, loff_t *ppos)
1086 {
1087 struct solo1_state *s = (struct solo1_state *)file->private_data;
1088 DECLARE_WAITQUEUE(wait, current);
1089  ssize_t ret;
1090 unsigned long flags;
1091 unsigned swptr;
1092 int cnt;
1093
1094 VALIDATE_STATE(s);
1095 if(ppos != &file->f_pos)
1096 return-ESPIPE;
1097 if(s->dma_dac.mapped)
1098 return-ENXIO;
1099 if(!s->dma_dac.ready && (ret =prog_dmabuf_dac(s)))
1100 return ret;
1101 if(!access_ok(VERIFY_READ, buffer, count))
1102 return-EFAULT;
1103 #if 0
1104 printk(KERN_DEBUG "solo1_write: reg 70: 0x%02x 71: 0x%02x 72: 0x%02x 74: 0x%02x 76: 0x%02x 78: 0x%02x 7A: 0x%02x\n"
1105  KERN_DEBUG "solo1_write: DMA: addr: 0x%08x cnt: 0x%04x stat: 0x%02x SBstat: 0x%02x\n",
1106 read_mixer(s,0x70),read_mixer(s,0x71),read_mixer(s,0x72),read_mixer(s,0x74),read_mixer(s,0x76),
1107 read_mixer(s,0x78),read_mixer(s,0x7a),inl(s->iobase),inw(s->iobase+4),inb(s->iobase+6),inb(s->sbbase+0xc));
1108 printk(KERN_DEBUG "solo1_write: reg 78: 0x%02x reg 7A: 0x%02x DMAcnt: 0x%04x DMAstat: 0x%02x SBstat: 0x%02x\n",
1109 read_mixer(s,0x78),read_mixer(s,0x7a),inw(s->iobase+4),inb(s->iobase+6),inb(s->sbbase+0xc));
1110 #endif
1111  ret =0;
1112 add_wait_queue(&s->dma_dac.wait, &wait);
1113 while(count >0) {
1114 spin_lock_irqsave(&s->lock, flags);
1115 if(s->dma_dac.count <0) {
1116  s->dma_dac.count =0;
1117  s->dma_dac.swptr = s->dma_dac.hwptr;
1118 }
1119  swptr = s->dma_dac.swptr;
1120  cnt = s->dma_dac.dmasize-swptr;
1121 if(s->dma_dac.count + cnt > s->dma_dac.dmasize)
1122  cnt = s->dma_dac.dmasize - s->dma_dac.count;
1123 if(cnt <=0)
1124 __set_current_state(TASK_INTERRUPTIBLE);
1125 spin_unlock_irqrestore(&s->lock, flags);
1126 if(cnt > count)
1127  cnt = count;
1128 if(cnt <=0) {
1129 start_dac(s);
1130 if(file->f_flags & O_NONBLOCK) {
1131 if(!ret)
1132  ret = -EAGAIN;
1133 break;
1134 }
1135 schedule();
1136 if(signal_pending(current)) {
1137 if(!ret)
1138  ret = -ERESTARTSYS;
1139 break;
1140 }
1141 continue;
1142 }
1143 if(copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1144 if(!ret)
1145  ret = -EFAULT;
1146 break;
1147 }
1148  swptr = (swptr + cnt) % s->dma_dac.dmasize;
1149 spin_lock_irqsave(&s->lock, flags);
1150  s->dma_dac.swptr = swptr;
1151  s->dma_dac.count += cnt;
1152  s->dma_dac.endcleared =0;
1153 spin_unlock_irqrestore(&s->lock, flags);
1154  count -= cnt;
1155  buffer += cnt;
1156  ret += cnt;
1157 start_dac(s);
1158 }
1159 remove_wait_queue(&s->dma_dac.wait, &wait);
1160 set_current_state(TASK_RUNNING);
1161 return ret;
1162 }
1163
1164 /* No kernel lock - we have our own spinlock */
1165 static unsigned intsolo1_poll(struct file *file,struct poll_table_struct *wait)
1166 {
1167 struct solo1_state *s = (struct solo1_state *)file->private_data;
1168 unsigned long flags;
1169 unsigned int mask =0;
1170
1171 VALIDATE_STATE(s);
1172 if(file->f_mode & FMODE_WRITE) {
1173 if(!s->dma_dac.ready &&prog_dmabuf_dac(s))
1174 return0;
1175 poll_wait(file, &s->dma_dac.wait, wait);
1176 }
1177 if(file->f_mode & FMODE_READ) {
1178 if(!s->dma_adc.ready &&prog_dmabuf_adc(s))
1179 return0;
1180 poll_wait(file, &s->dma_adc.wait, wait);
1181 }
1182 spin_lock_irqsave(&s->lock, flags);
1183 solo1_update_ptr(s);
1184 if(file->f_mode & FMODE_READ) {
1185 if(s->dma_adc.mapped) {
1186 if(s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1187  mask |= POLLIN | POLLRDNORM;
1188 }else{
1189 if(s->dma_adc.count >0)
1190  mask |= POLLIN | POLLRDNORM;
1191 }
1192 }
1193 if(file->f_mode & FMODE_WRITE) {
1194 if(s->dma_dac.mapped) {
1195 if(s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1196  mask |= POLLOUT | POLLWRNORM;
1197 }else{
1198 if((signed)s->dma_dac.dmasize > s->dma_dac.count)
1199  mask |= POLLOUT | POLLWRNORM;
1200 }
1201 }
1202 spin_unlock_irqrestore(&s->lock, flags);
1203 return mask;
1204 }
1205
1206
1207 static intsolo1_mmap(struct file *file,struct vm_area_struct *vma)
1208 {
1209 struct solo1_state *s = (struct solo1_state *)file->private_data;
1210 struct dmabuf *db;
1211 int ret = -EINVAL;
1212 unsigned long size;
1213
1214 VALIDATE_STATE(s);
1215 lock_kernel();
1216 if(vma->vm_flags & VM_WRITE) {
1217 if((ret =prog_dmabuf_dac(s)) !=0)
1218 goto out;
1219  db = &s->dma_dac;
1220 }else if(vma->vm_flags & VM_READ) {
1221 if((ret =prog_dmabuf_adc(s)) !=0)
1222 goto out;
1223  db = &s->dma_adc;
1224 }else
1225 goto out;
1226  ret = -EINVAL;
1227 if(vma->vm_pgoff !=0)
1228 goto out;
1229  size = vma->vm_end - vma->vm_start;
1230 if(size > (PAGE_SIZE << db->buforder))
1231 goto out;
1232  ret = -EAGAIN;
1233 if(remap_page_range(vma->vm_start,virt_to_phys(db->rawbuf), size, vma->vm_page_prot))
1234 goto out;
1235  db->mapped =1;
1236  ret =0;
1237 out:
1238 unlock_kernel();
1239 return ret;
1240 }
1241
1242 static intsolo1_ioctl(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
1243 {
1244 struct solo1_state *s = (struct solo1_state *)file->private_data;
1245 unsigned long flags;
1246  audio_buf_info abinfo;
1247  count_info cinfo;
1248 int val, mapped, ret, count;
1249 int div1, div2;
1250 unsigned rate1, rate2;
1251
1252 VALIDATE_STATE(s);
1253  mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1254 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1255 switch(cmd) {
1256 case OSS_GETVERSION:
1257 returnput_user(SOUND_VERSION, (int*)arg);
1258
1259 case SNDCTL_DSP_SYNC:
1260 if(file->f_mode & FMODE_WRITE)
1261 returndrain_dac(s,0/*file->f_flags & O_NONBLOCK*/);
1262 return0;
1263
1264 case SNDCTL_DSP_SETDUPLEX:
1265 return0;
1266
1267 case SNDCTL_DSP_GETCAPS:
1268 returnput_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int*)arg);
1269
1270 case SNDCTL_DSP_RESET:
1271 if(file->f_mode & FMODE_WRITE) {
1272 stop_dac(s);
1273 synchronize_irq();
1274  s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes =0;
1275 }
1276 if(file->f_mode & FMODE_READ) {
1277 stop_adc(s);
1278 synchronize_irq();
1279  s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes =0;
1280 }
1281 prog_codec(s);
1282 return0;
1283
1284 case SNDCTL_DSP_SPEED:
1285 if(get_user(val, (int*)arg))
1286 return-EFAULT;
1287 if(val >=0) {
1288 stop_adc(s);
1289 stop_dac(s);
1290  s->dma_adc.ready = s->dma_dac.ready =0;
1291 /* program sampling rates */
1292 if(val >48000)
1293  val =48000;
1294 if(val <6300)
1295  val =6300;
1296  div1 = (768000+ val /2) / val;
1297  rate1 = (768000+ div1 /2) / div1;
1298  div1 = -div1;
1299  div2 = (793800+ val /2) / val;
1300  rate2 = (793800+ div2 /2) / div2;
1301  div2 = (-div2) &0x7f;
1302 if(abs(val - rate2) <abs(val - rate1)) {
1303  rate1 = rate2;
1304  div1 = div2;
1305 }
1306  s->rate = rate1;
1307  s->clkdiv = div1;
1308 prog_codec(s);
1309 }
1310 returnput_user(s->rate, (int*)arg);
1311
1312 case SNDCTL_DSP_STEREO:
1313 if(get_user(val, (int*)arg))
1314 return-EFAULT;
1315 stop_adc(s);
1316 stop_dac(s);
1317  s->dma_adc.ready = s->dma_dac.ready =0;
1318 /* program channels */
1319  s->channels = val ?2:1;
1320 prog_codec(s);
1321 return0;
1322
1323 case SNDCTL_DSP_CHANNELS:
1324 if(get_user(val, (int*)arg))
1325 return-EFAULT;
1326 if(val !=0) {
1327 stop_adc(s);
1328 stop_dac(s);
1329  s->dma_adc.ready = s->dma_dac.ready =0;
1330 /* program channels */
1331  s->channels = (val >=2) ?2:1;
1332 prog_codec(s);
1333 }
1334 returnput_user(s->channels, (int*)arg);
1335
1336 case SNDCTL_DSP_GETFMTS:/* Returns a mask */
1337 returnput_user(AFMT_S16_LE|AFMT_U16_LE|AFMT_S8|AFMT_U8, (int*)arg);
1338
1339 case SNDCTL_DSP_SETFMT:/* Selects ONE fmt*/
1340 if(get_user(val, (int*)arg))
1341 return-EFAULT;
1342 if(val != AFMT_QUERY) {
1343 stop_adc(s);
1344 stop_dac(s);
1345  s->dma_adc.ready = s->dma_dac.ready =0;
1346 /* program format */
1347 if(val != AFMT_S16_LE && val != AFMT_U16_LE &&
1348  val != AFMT_S8 && val != AFMT_U8)
1349  val = AFMT_U8;
1350  s->fmt = val;
1351 prog_codec(s);
1352 }
1353 returnput_user(s->fmt, (int*)arg);
1354
1355 case SNDCTL_DSP_POST:
1356 return0;
1357
1358 case SNDCTL_DSP_GETTRIGGER:
1359  val =0;
1360 if(file->f_mode & s->ena & FMODE_READ)
1361  val |= PCM_ENABLE_INPUT;
1362 if(file->f_mode & s->ena & FMODE_WRITE)
1363  val |= PCM_ENABLE_OUTPUT;
1364 returnput_user(val, (int*)arg);
1365
1366 case SNDCTL_DSP_SETTRIGGER:
1367 if(get_user(val, (int*)arg))
1368 return-EFAULT;
1369 if(file->f_mode & FMODE_READ) {
1370 if(val & PCM_ENABLE_INPUT) {
1371 if(!s->dma_adc.ready && (ret =prog_dmabuf_adc(s)))
1372 return ret;
1373 start_adc(s);
1374 if(inb(s->ddmabase+15) &1)
1375 printk(KERN_ERR "solo1: cannot start recording, DDMA mask bit stuck at 1\n");
1376 }else
1377 stop_adc(s);
1378 }
1379 if(file->f_mode & FMODE_WRITE) {
1380 if(val & PCM_ENABLE_OUTPUT) {
1381 if(!s->dma_dac.ready && (ret =prog_dmabuf_dac(s)))
1382 return ret;
1383 start_dac(s);
1384 }else
1385 stop_dac(s);
1386 }
1387 return0;
1388
1389 case SNDCTL_DSP_GETOSPACE:
1390 if(!(file->f_mode & FMODE_WRITE))
1391 return-EINVAL;
1392 if(!s->dma_dac.ready && (ret =prog_dmabuf_dac(s)))
1393 return ret;
1394 spin_lock_irqsave(&s->lock, flags);
1395 solo1_update_ptr(s);
1396  abinfo.fragsize = s->dma_dac.fragsize;
1397  count = s->dma_dac.count;
1398 if(count <0)
1399  count =0;
1400  abinfo.bytes = s->dma_dac.dmasize - count;
1401  abinfo.fragstotal = s->dma_dac.numfrag;
1402  abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1403 spin_unlock_irqrestore(&s->lock, flags);
1404 returncopy_to_user((void*)arg, &abinfo,sizeof(abinfo)) ? -EFAULT :0;
1405
1406 case SNDCTL_DSP_GETISPACE:
1407 if(!(file->f_mode & FMODE_READ))
1408 return-EINVAL;
1409 if(!s->dma_adc.ready && (ret =prog_dmabuf_adc(s)))
1410 return ret;
1411 spin_lock_irqsave(&s->lock, flags);
1412 solo1_update_ptr(s);
1413  abinfo.fragsize = s->dma_adc.fragsize;
1414  abinfo.bytes = s->dma_adc.count;
1415  abinfo.fragstotal = s->dma_adc.numfrag;
1416  abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1417 spin_unlock_irqrestore(&s->lock, flags);
1418 returncopy_to_user((void*)arg, &abinfo,sizeof(abinfo)) ? -EFAULT :0;
1419
1420 case SNDCTL_DSP_NONBLOCK:
1421  file->f_flags |= O_NONBLOCK;
1422 return0;
1423
1424 case SNDCTL_DSP_GETODELAY:
1425 if(!(file->f_mode & FMODE_WRITE))
1426 return-EINVAL;
1427 if(!s->dma_dac.ready && (ret =prog_dmabuf_dac(s)))
1428 return ret;
1429 spin_lock_irqsave(&s->lock, flags);
1430 solo1_update_ptr(s);
1431  count = s->dma_dac.count;
1432 spin_unlock_irqrestore(&s->lock, flags);
1433 if(count <0)
1434  count =0;
1435 returnput_user(count, (int*)arg);
1436
1437 case SNDCTL_DSP_GETIPTR:
1438 if(!(file->f_mode & FMODE_READ))
1439 return-EINVAL;
1440 if(!s->dma_adc.ready && (ret =prog_dmabuf_adc(s)))
1441 return ret;
1442 spin_lock_irqsave(&s->lock, flags);
1443 solo1_update_ptr(s);
1444  cinfo.bytes = s->dma_adc.total_bytes;
1445  cinfo.blocks = s->dma_adc.count >> s->dma_adc.fragshift;
1446  cinfo.ptr = s->dma_adc.hwptr;
1447 if(s->dma_adc.mapped)
1448  s->dma_adc.count &= s->dma_adc.fragsize-1;
1449 spin_unlock_irqrestore(&s->lock, flags);
1450 returncopy_to_user((void*)arg, &cinfo,sizeof(cinfo));
1451
1452 case SNDCTL_DSP_GETOPTR:
1453 if(!(file->f_mode & FMODE_WRITE))
1454 return-EINVAL;
1455 if(!s->dma_dac.ready && (ret =prog_dmabuf_dac(s)))
1456 return ret;
1457 spin_lock_irqsave(&s->lock, flags);
1458 solo1_update_ptr(s);
1459  cinfo.bytes = s->dma_dac.total_bytes;
1460  count = s->dma_dac.count;
1461 if(count <0)
1462  count =0;
1463  cinfo.blocks = count >> s->dma_dac.fragshift;
1464  cinfo.ptr = s->dma_dac.hwptr;
1465 if(s->dma_dac.mapped)
1466  s->dma_dac.count &= s->dma_dac.fragsize-1;
1467 spin_unlock_irqrestore(&s->lock, flags);
1468 #if 0
1469 printk(KERN_DEBUG "esssolo1: GETOPTR: bytes %u blocks %u ptr %u, buforder %u numfrag %u fragshift %u\n"
1470  KERN_DEBUG "esssolo1: swptr %u count %u fragsize %u dmasize %u fragsamples %u\n",
1471  cinfo.bytes, cinfo.blocks, cinfo.ptr, s->dma_dac.buforder, s->dma_dac.numfrag, s->dma_dac.fragshift,
1472  s->dma_dac.swptr, s->dma_dac.count, s->dma_dac.fragsize, s->dma_dac.dmasize, s->dma_dac.fragsamples);
1473 #endif
1474 returncopy_to_user((void*)arg, &cinfo,sizeof(cinfo));
1475
1476 case SNDCTL_DSP_GETBLKSIZE:
1477 if(file->f_mode & FMODE_WRITE) {
1478 if((val =prog_dmabuf_dac(s)))
1479 return val;
1480 returnput_user(s->dma_dac.fragsize, (int*)arg);
1481 }
1482 if((val =prog_dmabuf_adc(s)))
1483 return val;
1484 returnput_user(s->dma_adc.fragsize, (int*)arg);
1485
1486 case SNDCTL_DSP_SETFRAGMENT:
1487 if(get_user(val, (int*)arg))
1488 return-EFAULT;
1489 if(file->f_mode & FMODE_READ) {
1490  s->dma_adc.ossfragshift = val &0xffff;
1491  s->dma_adc.ossmaxfrags = (val >>16) &0xffff;
1492 if(s->dma_adc.ossfragshift <4)
1493  s->dma_adc.ossfragshift =4;
1494 if(s->dma_adc.ossfragshift >15)
1495  s->dma_adc.ossfragshift =15;
1496 if(s->dma_adc.ossmaxfrags <4)
1497  s->dma_adc.ossmaxfrags =4;
1498 }
1499 if(file->f_mode & FMODE_WRITE) {
1500  s->dma_dac.ossfragshift = val &0xffff;
1501  s->dma_dac.ossmaxfrags = (val >>16) &0xffff;
1502 if(s->dma_dac.ossfragshift <4)
1503  s->dma_dac.ossfragshift =4;
1504 if(s->dma_dac.ossfragshift >15)
1505  s->dma_dac.ossfragshift =15;
1506 if(s->dma_dac.ossmaxfrags <4)
1507  s->dma_dac.ossmaxfrags =4;
1508 }
1509 return0;
1510
1511 case SNDCTL_DSP_SUBDIVIDE:
1512 if((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1513 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1514 return-EINVAL;
1515 if(get_user(val, (int*)arg))
1516 return-EFAULT;
1517 if(val !=1&& val !=2&& val !=4)
1518 return-EINVAL;
1519 if(file->f_mode & FMODE_READ)
1520  s->dma_adc.subdivision = val;
1521 if(file->f_mode & FMODE_WRITE)
1522  s->dma_dac.subdivision = val;
1523 return0;
1524
1525 case SOUND_PCM_READ_RATE:
1526 returnput_user(s->rate, (int*)arg);
1527
1528 case SOUND_PCM_READ_CHANNELS:
1529 returnput_user(s->channels, (int*)arg);
1530
1531 case SOUND_PCM_READ_BITS:
1532 returnput_user((s->fmt & (AFMT_S8|AFMT_U8)) ?8:16, (int*)arg);
1533
1534 case SOUND_PCM_WRITE_FILTER:
1535 case SNDCTL_DSP_SETSYNCRO:
1536 case SOUND_PCM_READ_FILTER:
1537 return-EINVAL;
1538
1539 }
1540 returnmixer_ioctl(s, cmd, arg);
1541 }
1542
1543 static intsolo1_release(struct inode *inode,struct file *file)
1544 {
1545 struct solo1_state *s = (struct solo1_state *)file->private_data;
1546
1547 VALIDATE_STATE(s);
1548 lock_kernel();
1549 if(file->f_mode & FMODE_WRITE)
1550 drain_dac(s, file->f_flags & O_NONBLOCK);
1551 down(&s->open_sem);
1552 if(file->f_mode & FMODE_WRITE) {
1553 stop_dac(s);
1554 outb(0, s->iobase+6);/* disable DMA */
1555 dealloc_dmabuf(s, &s->dma_dac);
1556 }
1557 if(file->f_mode & FMODE_READ) {
1558 stop_adc(s);
1559 outb(1, s->ddmabase+0xf);/* mask DMA channel */
1560 outb(0, s->ddmabase+0xd);/* DMA master clear */
1561 dealloc_dmabuf(s, &s->dma_adc);
1562 }
1563  s->open_mode &= ~(FMODE_READ | FMODE_WRITE);
1564 wake_up(&s->open_wait);
1565 up(&s->open_sem);
1566 unlock_kernel();
1567 return0;
1568 }
1569
1570 static intsolo1_open(struct inode *inode,struct file *file)
1571 {
1572 int minor =MINOR(inode->i_rdev);
1573 DECLARE_WAITQUEUE(wait, current);
1574 struct list_head *list;
1575 struct solo1_state *s;
1576
1577 for(list = devs.next; ; list = list->next) {
1578 if(list == &devs)
1579 return-ENODEV;
1580  s =list_entry(list,struct solo1_state, devs);
1581 if(!((s->dev_audio ^ minor) & ~0xf))
1582 break;
1583 }
1584 VALIDATE_STATE(s);
1585  file->private_data = s;
1586 /* wait for device to become free */
1587 down(&s->open_sem);
1588 while(s->open_mode & (FMODE_READ | FMODE_WRITE)) {
1589 if(file->f_flags & O_NONBLOCK) {
1590 up(&s->open_sem);
1591 return-EBUSY;
1592 }
1593 add_wait_queue(&s->open_wait, &wait);
1594 __set_current_state(TASK_INTERRUPTIBLE);
1595 up(&s->open_sem);
1596 schedule();
1597 remove_wait_queue(&s->open_wait, &wait);
1598 set_current_state(TASK_RUNNING);
1599 if(signal_pending(current))
1600 return-ERESTARTSYS;
1601 down(&s->open_sem);
1602 }
1603  s->fmt = AFMT_U8;
1604  s->channels =1;
1605  s->rate =8000;
1606  s->clkdiv =96|0x80;
1607  s->ena =0;
1608  s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision =0;
1609  s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision =0;
1610  s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1611 up(&s->open_sem);
1612 prog_codec(s);
1613 return0;
1614 }
1615
1616 static/*const*/struct file_operations solo1_audio_fops = {
1617  owner: THIS_MODULE,
1618  llseek: solo1_llseek,
1619  read: solo1_read,
1620  write: solo1_write,
1621  poll: solo1_poll,
1622  ioctl: solo1_ioctl,
1623  mmap: solo1_mmap,
1624  open: solo1_open,
1625  release: solo1_release,
1626 };
1627
1628 /* --------------------------------------------------------------------- */
1629
1630 /* hold spinlock for the following! */
1631 static voidsolo1_handle_midi(struct solo1_state *s)
1632 {
1633 unsigned char ch;
1634 int wake;
1635
1636 if(!(s->mpubase))
1637 return;
1638  wake =0;
1639 while(!(inb(s->mpubase+1) &0x80)) {
1640  ch =inb(s->mpubase);
1641 if(s->midi.icnt < MIDIINBUF) {
1642  s->midi.ibuf[s->midi.iwr] = ch;
1643  s->midi.iwr = (s->midi.iwr +1) % MIDIINBUF;
1644  s->midi.icnt++;
1645 }
1646  wake =1;
1647 }
1648 if(wake)
1649 wake_up(&s->midi.iwait);
1650  wake =0;
1651 while(!(inb(s->mpubase+1) &0x40) && s->midi.ocnt >0) {
1652 outb(s->midi.obuf[s->midi.ord], s->mpubase);
1653  s->midi.ord = (s->midi.ord +1) % MIDIOUTBUF;
1654  s->midi.ocnt--;
1655 if(s->midi.ocnt < MIDIOUTBUF-16)
1656  wake =1;
1657 }
1658 if(wake)
1659 wake_up(&s->midi.owait);
1660 }
1661
1662 static voidsolo1_interrupt(int irq,void*dev_id,struct pt_regs *regs)
1663 {
1664 struct solo1_state *s = (struct solo1_state *)dev_id;
1665 unsigned int intsrc;
1666
1667 /* fastpath out, to ease interrupt sharing */
1668  intsrc =inb(s->iobase+7);/* get interrupt source(s) */
1669 if(!intsrc)
1670 return;
1671 (void)inb(s->sbbase+0xe);/* clear interrupt */
1672 spin_lock(&s->lock);
1673 /* clear audio interrupts first */
1674 if(intsrc &0x20)
1675 write_mixer(s,0x7a,read_mixer(s,0x7a) &0x7f);
1676 solo1_update_ptr(s);
1677 solo1_handle_midi(s);
1678 spin_unlock(&s->lock);
1679 }
1680
1681 static voidsolo1_midi_timer(unsigned long data)
1682 {
1683 struct solo1_state *s = (struct solo1_state *)data;
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&s->lock, flags);
1687 solo1_handle_midi(s);
1688 spin_unlock_irqrestore(&s->lock, flags);
1689  s->midi.timer.expires = jiffies+1;
1690 add_timer(&s->midi.timer);
1691 }
1692
1693 /* --------------------------------------------------------------------- */
1694
1695 static ssize_t solo1_midi_read(struct file *file,char*buffer,size_t count, loff_t *ppos)
1696 {
1697 struct solo1_state *s = (struct solo1_state *)file->private_data;
1698 DECLARE_WAITQUEUE(wait, current);
1699  ssize_t ret;
1700 unsigned long flags;
1701 unsigned ptr;
1702 int cnt;
1703
1704 VALIDATE_STATE(s);
1705 if(ppos != &file->f_pos)
1706 return-ESPIPE;
1707 if(!access_ok(VERIFY_WRITE, buffer, count))
1708 return-EFAULT;
1709 if(count ==0)
1710 return0;
1711  ret =0;
1712 add_wait_queue(&s->midi.iwait, &wait);
1713 while(count >0) {
1714 spin_lock_irqsave(&s->lock, flags);
1715  ptr = s->midi.ird;
1716  cnt = MIDIINBUF - ptr;
1717 if(s->midi.icnt < cnt)
1718  cnt = s->midi.icnt;
1719 if(cnt <=0)
1720 __set_current_state(TASK_INTERRUPTIBLE);
1721 spin_unlock_irqrestore(&s->lock, flags);
1722 if(cnt > count)
1723  cnt = count;
1724 if(cnt <=0) {
1725 if(file->f_flags & O_NONBLOCK) {
1726 if(!ret)
1727  ret = -EAGAIN;
1728 break;
1729 }
1730 schedule();
1731 if(signal_pending(current)) {
1732 if(!ret)
1733  ret = -ERESTARTSYS;
1734 break;
1735 }
1736 continue;
1737 }
1738 if(copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
1739 if(!ret)
1740  ret = -EFAULT;
1741 break;
1742 }
1743  ptr = (ptr + cnt) % MIDIINBUF;
1744 spin_lock_irqsave(&s->lock, flags);
1745  s->midi.ird = ptr;
1746  s->midi.icnt -= cnt;
1747 spin_unlock_irqrestore(&s->lock, flags);
1748  count -= cnt;
1749  buffer += cnt;
1750  ret += cnt;
1751 break;
1752 }
1753 __set_current_state(TASK_RUNNING);
1754 remove_wait_queue(&s->midi.iwait, &wait);
1755 return ret;
1756 }
1757
1758 static ssize_t solo1_midi_write(struct file *file,const char*buffer,size_t count, loff_t *ppos)
1759 {
1760 struct solo1_state *s = (struct solo1_state *)file->private_data;
1761 DECLARE_WAITQUEUE(wait, current);
1762  ssize_t ret;
1763 unsigned long flags;
1764 unsigned ptr;
1765 int cnt;
1766
1767 VALIDATE_STATE(s);
1768 if(ppos != &file->f_pos)
1769 return-ESPIPE;
1770 if(!access_ok(VERIFY_READ, buffer, count))
1771 return-EFAULT;
1772 if(count ==0)
1773 return0;
1774  ret =0;
1775 add_wait_queue(&s->midi.owait, &wait);
1776 while(count >0) {
1777 spin_lock_irqsave(&s->lock, flags);
1778  ptr = s->midi.owr;
1779  cnt = MIDIOUTBUF - ptr;
1780 if(s->midi.ocnt + cnt > MIDIOUTBUF)
1781  cnt = MIDIOUTBUF - s->midi.ocnt;
1782 if(cnt <=0) {
1783 __set_current_state(TASK_INTERRUPTIBLE);
1784 solo1_handle_midi(s);
1785 }
1786 spin_unlock_irqrestore(&s->lock, flags);
1787 if(cnt > count)
1788  cnt = count;
1789 if(cnt <=0) {
1790 if(file->f_flags & O_NONBLOCK) {
1791 if(!ret)
1792  ret = -EAGAIN;
1793 break;
1794 }
1795 schedule();
1796 if(signal_pending(current)) {
1797 if(!ret)
1798  ret = -ERESTARTSYS;
1799 break;
1800 }
1801 continue;
1802 }
1803 if(copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
1804 if(!ret)
1805  ret = -EFAULT;
1806 break;
1807 }
1808  ptr = (ptr + cnt) % MIDIOUTBUF;
1809 spin_lock_irqsave(&s->lock, flags);
1810  s->midi.owr = ptr;
1811  s->midi.ocnt += cnt;
1812 spin_unlock_irqrestore(&s->lock, flags);
1813  count -= cnt;
1814  buffer += cnt;
1815  ret += cnt;
1816 spin_lock_irqsave(&s->lock, flags);
1817 solo1_handle_midi(s);
1818 spin_unlock_irqrestore(&s->lock, flags);
1819 }
1820 __set_current_state(TASK_RUNNING);
1821 remove_wait_queue(&s->midi.owait, &wait);
1822 return ret;
1823 }
1824
1825 /* No kernel lock - we have our own spinlock */
1826 static unsigned intsolo1_midi_poll(struct file *file,struct poll_table_struct *wait)
1827 {
1828 struct solo1_state *s = (struct solo1_state *)file->private_data;
1829 unsigned long flags;
1830 unsigned int mask =0;
1831
1832 VALIDATE_STATE(s);
1833 if(file->f_flags & FMODE_WRITE)
1834 poll_wait(file, &s->midi.owait, wait);
1835 if(file->f_flags & FMODE_READ)
1836 poll_wait(file, &s->midi.iwait, wait);
1837 spin_lock_irqsave(&s->lock, flags);
1838 if(file->f_flags & FMODE_READ) {
1839 if(s->midi.icnt >0)
1840  mask |= POLLIN | POLLRDNORM;
1841 }
1842 if(file->f_flags & FMODE_WRITE) {
1843 if(s->midi.ocnt < MIDIOUTBUF)
1844  mask |= POLLOUT | POLLWRNORM;
1845 }
1846 spin_unlock_irqrestore(&s->lock, flags);
1847 return mask;
1848 }
1849
1850 static intsolo1_midi_open(struct inode *inode,struct file *file)
1851 {
1852 int minor =MINOR(inode->i_rdev);
1853 DECLARE_WAITQUEUE(wait, current);
1854 unsigned long flags;
1855 struct list_head *list;
1856 struct solo1_state *s;
1857
1858 for(list = devs.next; ; list = list->next) {
1859 if(list == &devs)
1860 return-ENODEV;
1861  s =list_entry(list,struct solo1_state, devs);
1862 if(s->dev_midi == minor)
1863 break;
1864 }
1865 VALIDATE_STATE(s);
1866  file->private_data = s;
1867 /* wait for device to become free */
1868 down(&s->open_sem);
1869 while(s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
1870 if(file->f_flags & O_NONBLOCK) {
1871 up(&s->open_sem);
1872 return-EBUSY;
1873 }
1874 add_wait_queue(&s->open_wait, &wait);
1875 __set_current_state(TASK_INTERRUPTIBLE);
1876 up(&s->open_sem);
1877 schedule();
1878 remove_wait_queue(&s->open_wait, &wait);
1879 set_current_state(TASK_RUNNING);
1880 if(signal_pending(current))
1881 return-ERESTARTSYS;
1882 down(&s->open_sem);
1883 }
1884 spin_lock_irqsave(&s->lock, flags);
1885 if(!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1886  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
1887  s->midi.ord = s->midi.owr = s->midi.ocnt =0;
1888 outb(0xff, s->mpubase+1);/* reset command */
1889 outb(0x3f, s->mpubase+1);/* uart command */
1890 if(!(inb(s->mpubase+1) &0x80))
1891 inb(s->mpubase);
1892  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
1893 outb(0xb0, s->iobase +7);/* enable A1, A2, MPU irq's */
1894 init_timer(&s->midi.timer);
1895  s->midi.timer.expires = jiffies+1;
1896  s->midi.timer.data = (unsigned long)s;
1897  s->midi.timer.function = solo1_midi_timer;
1898 add_timer(&s->midi.timer);
1899 }
1900 if(file->f_mode & FMODE_READ) {
1901  s->midi.ird = s->midi.iwr = s->midi.icnt =0;
1902 }
1903 if(file->f_mode & FMODE_WRITE) {
1904  s->midi.ord = s->midi.owr = s->midi.ocnt =0;
1905 }
1906 spin_unlock_irqrestore(&s->lock, flags);
1907  s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
1908 up(&s->open_sem);
1909 return0;
1910 }
1911
1912 static intsolo1_midi_release(struct inode *inode,struct file *file)
1913 {
1914 struct solo1_state *s = (struct solo1_state *)file->private_data;
1915 DECLARE_WAITQUEUE(wait, current);
1916 unsigned long flags;
1917 unsigned count, tmo;
1918
1919 VALIDATE_STATE(s);
1920
1921 lock_kernel();
1922 if(file->f_mode & FMODE_WRITE) {
1923 add_wait_queue(&s->midi.owait, &wait);
1924 for(;;) {
1925 __set_current_state(TASK_INTERRUPTIBLE);
1926 spin_lock_irqsave(&s->lock, flags);
1927  count = s->midi.ocnt;
1928 spin_unlock_irqrestore(&s->lock, flags);
1929 if(count <=0)
1930 break;
1931 if(signal_pending(current))
1932 break;
1933 if(file->f_flags & O_NONBLOCK) {
1934 remove_wait_queue(&s->midi.owait, &wait);
1935 set_current_state(TASK_RUNNING);
1936 return-EBUSY;
1937 }
1938  tmo = (count * HZ) /3100;
1939 if(!schedule_timeout(tmo ? :1) && tmo)
1940 printk(KERN_DEBUG "solo1: midi timed out??\n");
1941 }
1942 remove_wait_queue(&s->midi.owait, &wait);
1943 set_current_state(TASK_RUNNING);
1944 }
1945 down(&s->open_sem);
1946  s->open_mode &= (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE);
1947 spin_lock_irqsave(&s->lock, flags);
1948 if(!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
1949 outb(0x30, s->iobase +7);/* enable A1, A2 irq's */
1950 del_timer(&s->midi.timer);
1951 }
1952 spin_unlock_irqrestore(&s->lock, flags);
1953 wake_up(&s->open_wait);
1954 up(&s->open_sem);
1955 unlock_kernel();
1956 return0;
1957 }
1958
1959 static/*const*/struct file_operations solo1_midi_fops = {
1960  owner: THIS_MODULE,
1961  llseek: solo1_llseek,
1962  read: solo1_midi_read,
1963  write: solo1_midi_write,
1964  poll: solo1_midi_poll,
1965  open: solo1_midi_open,
1966  release: solo1_midi_release,
1967 };
1968
1969 /* --------------------------------------------------------------------- */
1970
1971 static intsolo1_dmfm_ioctl(struct inode *inode,struct file *file,unsigned int cmd,unsigned long arg)
1972 {
1973 static const unsigned char op_offset[18] = {
1974 0x00,0x01,0x02,0x03,0x04,0x05,
1975 0x08,0x09,0x0A,0x0B,0x0C,0x0D,
1976 0x10,0x11,0x12,0x13,0x14,0x15
1977 };
1978 struct solo1_state *s = (struct solo1_state *)file->private_data;
1979 struct dm_fm_voice v;
1980 struct dm_fm_note n;
1981 struct dm_fm_params p;
1982 unsigned int io;
1983 unsigned int regb;
1984
1985 switch(cmd) {
1986 case FM_IOCTL_RESET:
1987 for(regb =0xb0; regb <0xb9; regb++) {
1988 outb(regb, s->sbbase);
1989 outb(0, s->sbbase+1);
1990 outb(regb, s->sbbase+2);
1991 outb(0, s->sbbase+3);
1992 }
1993 return0;
1994
1995 case FM_IOCTL_PLAY_NOTE:
1996 if(copy_from_user(&n, (void*)arg,sizeof(n)))
1997 return-EFAULT;
1998 if(n.voice >=18)
1999 return-EINVAL;
2000 if(n.voice >=9) {
2001  regb = n.voice -9;
2002  io = s->sbbase+2;
2003 }else{
2004  regb = n.voice;
2005  io = s->sbbase;
2006 }
2007 outb(0xa0+ regb, io);
2008 outb(n.fnum &0xff, io+1);
2009 outb(0xb0+ regb, io);
2010 outb(((n.fnum >>8) &3) | ((n.octave &7) <<2) | ((n.key_on &1) <<5), io+1);
2011 return0;
2012
2013 case FM_IOCTL_SET_VOICE:
2014 if(copy_from_user(&v, (void*)arg,sizeof(v)))
2015 return-EFAULT;
2016 if(v.voice >=18)
2017 return-EINVAL;
2018  regb = op_offset[v.voice];
2019  io = s->sbbase + ((v.op &1) <<1);
2020 outb(0x20+ regb, io);
2021 outb(((v.am &1) <<7) | ((v.vibrato &1) <<6) | ((v.do_sustain &1) <<5) |
2022 ((v.kbd_scale &1) <<4) | (v.harmonic &0xf), io+1);
2023 outb(0x40+ regb, io);
2024 outb(((v.scale_level &0x3) <<6) | (v.volume &0x3f), io+1);
2025 outb(0x60+ regb, io);
2026 outb(((v.attack &0xf) <<4) | (v.decay &0xf), io+1);
2027 outb(0x80+ regb, io);
2028 outb(((v.sustain &0xf) <<4) | (v.release &0xf), io+1);
2029 outb(0xe0+ regb, io);
2030 outb(v.waveform &0x7, io+1);
2031 if(n.voice >=9) {
2032  regb = n.voice -9;
2033  io = s->sbbase+2;
2034 }else{
2035  regb = n.voice;
2036  io = s->sbbase;
2037 }
2038 outb(0xc0+ regb, io);
2039 outb(((v.right &1) <<5) | ((v.left &1) <<4) | ((v.feedback &7) <<1) |
2040 (v.connection &1), io+1);
2041 return0;
2042
2043 case FM_IOCTL_SET_PARAMS:
2044 if(copy_from_user(&p, (void*)arg,sizeof(p)))
2045 return-EFAULT;
2046 outb(0x08, s->sbbase);
2047 outb((p.kbd_split &1) <<6, s->sbbase+1);
2048 outb(0xbd, s->sbbase);
2049 outb(((p.am_depth &1) <<7) | ((p.vib_depth &1) <<6) | ((p.rhythm &1) <<5) | ((p.bass &1) <<4) |
2050 ((p.snare &1) <<3) | ((p.tomtom &1) <<2) | ((p.cymbal &1) <<1) | (p.hihat &1), s->sbbase+1);
2051 return0;
2052
2053 case FM_IOCTL_SET_OPL:
2054 outb(4, s->sbbase+2);
2055 outb(arg, s->sbbase+3);
2056 return0;
2057
2058 case FM_IOCTL_SET_MODE:
2059 outb(5, s->sbbase+2);
2060 outb(arg &1, s->sbbase+3);
2061 return0;
2062
2063 default:
2064 return-EINVAL;
2065 }
2066 }
2067
2068 static intsolo1_dmfm_open(struct inode *inode,struct file *file)
2069 {
2070 int minor =MINOR(inode->i_rdev);
2071 DECLARE_WAITQUEUE(wait, current);
2072 struct list_head *list;
2073 struct solo1_state *s;
2074
2075 for(list = devs.next; ; list = list->next) {
2076 if(list == &devs)
2077 return-ENODEV;
2078  s =list_entry(list,struct solo1_state, devs);
2079 if(s->dev_dmfm == minor)
2080 break;
2081 }
2082 VALIDATE_STATE(s);
2083  file->private_data = s;
2084 /* wait for device to become free */
2085 down(&s->open_sem);
2086 while(s->open_mode & FMODE_DMFM) {
2087 if(file->f_flags & O_NONBLOCK) {
2088 up(&s->open_sem);
2089 return-EBUSY;
2090 }
2091 add_wait_queue(&s->open_wait, &wait);
2092 __set_current_state(TASK_INTERRUPTIBLE);
2093 up(&s->open_sem);
2094 schedule();
2095 remove_wait_queue(&s->open_wait, &wait);
2096 set_current_state(TASK_RUNNING);
2097 if(signal_pending(current))
2098 return-ERESTARTSYS;
2099 down(&s->open_sem);
2100 }
2101 if(!request_region(s->sbbase, FMSYNTH_EXTENT,"ESS Solo1")) {
2102 up(&s->open_sem);
2103 printk(KERN_ERR "solo1: FM synth io ports in use, opl3 loaded?\n");
2104 return-EBUSY;
2105 }
2106 /* init the stuff */
2107 outb(1, s->sbbase);
2108 outb(0x20, s->sbbase+1);/* enable waveforms */
2109 outb(4, s->sbbase+2);
2110 outb(0, s->sbbase+3);/* no 4op enabled */
2111 outb(5, s->sbbase+2);
2112 outb(1, s->sbbase+3);/* enable OPL3 */
2113  s->open_mode |= FMODE_DMFM;
2114 up(&s->open_sem);
2115 return0;
2116 }
2117
2118 static intsolo1_dmfm_release(struct inode *inode,struct file *file)
2119 {
2120 struct solo1_state *s = (struct solo1_state *)file->private_data;
2121 unsigned int regb;
2122
2123 VALIDATE_STATE(s);
2124 lock_kernel();
2125 down(&s->open_sem);
2126  s->open_mode &= ~FMODE_DMFM;
2127 for(regb =0xb0; regb <0xb9; regb++) {
2128 outb(regb, s->sbbase);
2129 outb(0, s->sbbase+1);
2130 outb(regb, s->sbbase+2);
2131 outb(0, s->sbbase+3);
2132 }
2133 release_region(s->sbbase, FMSYNTH_EXTENT);
2134 wake_up(&s->open_wait);
2135 up(&s->open_sem);
2136 unlock_kernel();
2137 return0;
2138 }
2139
2140 static/*const*/struct file_operations solo1_dmfm_fops = {
2141  owner: THIS_MODULE,
2142  llseek: solo1_llseek,
2143  ioctl: solo1_dmfm_ioctl,
2144  open: solo1_dmfm_open,
2145  release: solo1_dmfm_release,
2146 };
2147
2148 /* --------------------------------------------------------------------- */
2149
2150 static struct initvol {
2151 int mixch;
2152 int vol;
2153 } initvol[] __initdata = {
2154 { SOUND_MIXER_WRITE_VOLUME,0x4040},
2155 { SOUND_MIXER_WRITE_PCM,0x4040},
2156 { SOUND_MIXER_WRITE_SYNTH,0x4040},
2157 { SOUND_MIXER_WRITE_CD,0x4040},
2158 { SOUND_MIXER_WRITE_LINE,0x4040},
2159 { SOUND_MIXER_WRITE_LINE1,0x4040},
2160 { SOUND_MIXER_WRITE_LINE2,0x4040},
2161 { SOUND_MIXER_WRITE_RECLEV,0x4040},
2162 { SOUND_MIXER_WRITE_SPEAKER,0x4040},
2163 { SOUND_MIXER_WRITE_MIC,0x4040}
2164 };
2165
2166 static intsetup_solo1(struct solo1_state *s)
2167 {
2168 struct pci_dev *pcidev = s->dev;
2169  mm_segment_t fs;
2170 int i, val;
2171
2172 /* initialize DDMA base address */
2173 printk(KERN_DEBUG "solo1: ddma base address: 0x%lx\n", s->ddmabase);
2174 pci_write_config_word(pcidev,0x60, (s->ddmabase & (~0xf)) |1);
2175 /* set DMA policy to DDMA, IRQ emulation off (CLKRUN disabled for now) */
2176 pci_write_config_dword(pcidev,0x50,0);
2177 /* disable legacy audio address decode */
2178 pci_write_config_word(pcidev,0x40,0x907f);
2179
2180 /* initialize the chips */
2181 if(!reset_ctrl(s)) {
2182 printk(KERN_ERR "esssolo1: cannot reset controller\n");
2183 return-1;
2184 }
2185 outb(0xb0, s->iobase+7);/* enable A1, A2, MPU irq's */
2186
2187 /* initialize mixer regs */
2188 write_mixer(s,0x7f,0);/* disable music digital recording */
2189 write_mixer(s,0x7d,0x0c);/* enable mic preamp, MONO_OUT is 2nd DAC right channel */
2190 write_mixer(s,0x64,0x45);/* volume control */
2191 write_mixer(s,0x48,0x10);/* enable music DAC/ES6xx interface */
2192 write_mixer(s,0x50,0);/* disable spatializer */
2193 write_mixer(s,0x52,0);
2194 write_mixer(s,0x14,0);/* DAC1 minimum volume */
2195 write_mixer(s,0x71,0x20);/* enable new 0xA1 reg format */
2196 outb(0, s->ddmabase+0xd);/* DMA master clear */
2197 outb(1, s->ddmabase+0xf);/* mask channel */
2198 /*outb(0, s->ddmabase+0x8);*//* enable controller (enable is low active!!) */
2199
2200 pci_set_master(pcidev);/* enable bus mastering */
2201
2202  fs =get_fs();
2203 set_fs(KERNEL_DS);
2204  val = SOUND_MASK_LINE;
2205 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2206 for(i =0; i <sizeof(initvol)/sizeof(initvol[0]); i++) {
2207  val = initvol[i].vol;
2208 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2209 }
2210  val =1;/* enable mic preamp */
2211 mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long)&val);
2212 set_fs(fs);
2213 return0;
2214 }
2215
2216 static intsolo1_pm_callback(struct pm_dev *dev, pm_request_t rqst,void*data)
2217 {
2218 struct solo1_state *s = (struct solo1_state*) dev->data;
2219 if(s) {
2220 switch(rqst) {
2221 case PM_RESUME:
2222 setup_solo1(s);
2223 break;
2224
2225 case PM_SUSPEND:
2226 outb(0, s->iobase+6);
2227 /* DMA master clear */
2228 outb(0, s->ddmabase+0xd);
2229 /* reset sequencer and FIFO */
2230 outb(3, s->sbbase+6);
2231 /* turn off DDMA controller address space */
2232 pci_write_config_word(s->dev,0x60,0);
2233 break;
2234 }
2235 }
2236 return0;
2237 }
2238
2239
2240 #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
2241  (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
2242
2243 static int __devinit solo1_probe(struct pci_dev *pcidev,const struct pci_device_id *pciid)
2244 {
2245 struct solo1_state *s;
2246 struct pm_dev *pmdev;
2247  dma_addr_t dma_mask;
2248
2249 if(!RSRCISIOREGION(pcidev,0) ||
2250 !RSRCISIOREGION(pcidev,1) ||
2251 !RSRCISIOREGION(pcidev,2) ||
2252 !RSRCISIOREGION(pcidev,3))
2253 return-1;
2254 if(pcidev->irq ==0)
2255 return-1;
2256 if(pci_dma_supported(pcidev,0x00ffffff)) {
2257  dma_mask =0x00ffffff;/* this enables playback and recording */
2258 }else if(pci_dma_supported(pcidev,0xffffffff)) {
2259  dma_mask =0xffffffff;/* this enables only playback, as the recording BMDMA can handle only 24bits */
2260 }else{
2261 printk(KERN_WARNING "solo1: architecture does not support 24bit or 32bit PCI busmaster DMA\n");
2262 return-1;
2263 }
2264 if(!(s =kmalloc(sizeof(struct solo1_state), GFP_KERNEL))) {
2265 printk(KERN_WARNING "solo1: out of memory\n");
2266 return-1;
2267 }
2268 memset(s,0,sizeof(struct solo1_state));
2269 init_waitqueue_head(&s->dma_adc.wait);
2270 init_waitqueue_head(&s->dma_dac.wait);
2271 init_waitqueue_head(&s->open_wait);
2272 init_waitqueue_head(&s->midi.iwait);
2273 init_waitqueue_head(&s->midi.owait);
2274 init_MUTEX(&s->open_sem);
2275 spin_lock_init(&s->lock);
2276  s->magic = SOLO1_MAGIC;
2277  s->dev = pcidev;
2278  s->iobase =pci_resource_start(pcidev,0);
2279  s->sbbase =pci_resource_start(pcidev,1);
2280  s->vcbase =pci_resource_start(pcidev,2);
2281  s->ddmabase = s->vcbase + DDMABASE_OFFSET;
2282  s->mpubase =pci_resource_start(pcidev,3);
2283  s->gpbase =pci_resource_start(pcidev,4);
2284  s->irq = pcidev->irq;
2285 if(!request_region(s->iobase, IOBASE_EXTENT,"ESS Solo1")) {
2286 printk(KERN_ERR "solo1: io ports in use\n");
2287 goto err_region1;
2288 }
2289 if(!request_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT,"ESS Solo1")) {
2290 printk(KERN_ERR "solo1: io ports in use\n");
2291 goto err_region2;
2292 }
2293 if(!request_region(s->ddmabase, DDMABASE_EXTENT,"ESS Solo1")) {
2294 printk(KERN_ERR "solo1: io ports in use\n");
2295 goto err_region3;
2296 }
2297 if(!request_region(s->mpubase, MPUBASE_EXTENT,"ESS Solo1")) {
2298 printk(KERN_ERR "solo1: io ports in use\n");
2299 goto err_region4;
2300 }
2301 if(request_irq(s->irq, solo1_interrupt, SA_SHIRQ,"ESS Solo1", s)) {
2302 printk(KERN_ERR "solo1: irq %u in use\n", s->irq);
2303 goto err_irq;
2304 }
2305 if(pci_enable_device(pcidev))
2306 goto err_irq;
2307 printk(KERN_INFO "solo1: joystick port at %#lx\n", s->gpbase+1);
2308 /* register devices */
2309 if((s->dev_audio =register_sound_dsp(&solo1_audio_fops, -1)) <0)
2310 goto err_dev1;
2311 if((s->dev_mixer =register_sound_mixer(&solo1_mixer_fops, -1)) <0)
2312 goto err_dev2;
2313 if((s->dev_midi =register_sound_midi(&solo1_midi_fops, -1)) <0)
2314 goto err_dev3;
2315 if((s->dev_dmfm =register_sound_special(&solo1_dmfm_fops,15/* ?? */)) <0)
2316 goto err_dev4;
2317 if(setup_solo1(s))
2318 goto err;
2319 /* store it in the driver field */
2320 pci_set_drvdata(pcidev, s);
2321  pcidev->dma_mask = dma_mask;
2322 /* put it into driver list */
2323 list_add_tail(&s->devs, &devs);
2324
2325  pmdev =pm_register(PM_PCI_DEV,PM_PCI_ID(pcidev), solo1_pm_callback);
2326 if(pmdev)
2327  pmdev->data = s;
2328
2329 return0;
2330
2331  err:
2332 unregister_sound_dsp(s->dev_dmfm);
2333  err_dev4:
2334 unregister_sound_dsp(s->dev_midi);
2335  err_dev3:
2336 unregister_sound_mixer(s->dev_mixer);
2337  err_dev2:
2338 unregister_sound_dsp(s->dev_audio);
2339  err_dev1:
2340 printk(KERN_ERR "solo1: initialisation error\n");
2341 free_irq(s->irq, s);
2342  err_irq:
2343 release_region(s->iobase, IOBASE_EXTENT);
2344  err_region4:
2345 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2346  err_region3:
2347 release_region(s->ddmabase, DDMABASE_EXTENT);
2348  err_region2:
2349 release_region(s->mpubase, MPUBASE_EXTENT);
2350  err_region1:
2351 kfree(s);
2352 return-1;
2353 }
2354
2355 static void __devinit solo1_remove(struct pci_dev *dev)
2356 {
2357 struct solo1_state *s =pci_get_drvdata(dev);
2358
2359 if(!s)
2360 return;
2361 list_del(&s->devs);
2362 /* stop DMA controller */
2363 outb(0, s->iobase+6);
2364 outb(0, s->ddmabase+0xd);/* DMA master clear */
2365 outb(3, s->sbbase+6);/* reset sequencer and FIFO */
2366 synchronize_irq();
2367 pci_write_config_word(s->dev,0x60,0);/* turn off DDMA controller address space */
2368 free_irq(s->irq, s);
2369 release_region(s->iobase, IOBASE_EXTENT);
2370 release_region(s->sbbase+FMSYNTH_EXTENT, SBBASE_EXTENT-FMSYNTH_EXTENT);
2371 release_region(s->ddmabase, DDMABASE_EXTENT);
2372 release_region(s->mpubase, MPUBASE_EXTENT);
2373 unregister_sound_dsp(s->dev_audio);
2374 unregister_sound_mixer(s->dev_mixer);
2375 unregister_sound_midi(s->dev_midi);
2376 unregister_sound_special(s->dev_dmfm);
2377 kfree(s);
2378 pci_set_drvdata(dev, NULL);
2379 }
2380
2381 static struct pci_device_id id_table[] __devinitdata = {
2382 { PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_SOLO1, PCI_ANY_ID, PCI_ANY_ID,0,0},
2383 {0, }
2384 };
2385
2386 MODULE_DEVICE_TABLE(pci, id_table);
2387
2388 static struct pci_driver solo1_driver = {
2389  name:"ESS Solo1",
2390  id_table: id_table,
2391  probe: solo1_probe,
2392  remove: solo1_remove
2393 };
2394
2395
2396 static int __init init_solo1(void)
2397 {
2398 if(!pci_present())/* No PCI bus in this machine! */
2399 return-ENODEV;
2400 printk(KERN_INFO "solo1: version v0.16 time " __TIME__ " " __DATE__ "\n");
2401 if(!pci_register_driver(&solo1_driver)) {
2402 pci_unregister_driver(&solo1_driver);
2403 return-ENODEV;
2404 }
2405 return0;
2406 }
2407
2408 /* --------------------------------------------------------------------- */
2409
2410 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2411 MODULE_DESCRIPTION("ESS Solo1 Driver");
2412
2413 static void __exit cleanup_solo1(void)
2414 {
2415 printk(KERN_INFO "solo1: unloading\n");
2416 pci_unregister_driver(&solo1_driver);
2417 pm_unregister_all(solo1_pm_callback);
2418 }
2419
2420 /* --------------------------------------------------------------------- */
2421
2422 module_init(init_solo1);
2423 module_exit(cleanup_solo1);
2424