include/net/irda/pc87108.h

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 1 /*********************************************************************
 2  *
 3  * Filename: pc87108.h
 4  * Version:
 5  * Description:
 6  * Status: Experimental.
 7  * Author: Dag Brattli <dagb@cs.uit.no>
 8  * Created at: Fri Nov 13 14:37:40 1998
 9  * Modified at: Mon Jan 25 23:10:25 1999
 10  * Modified by: Dag Brattli <dagb@cs.uit.no>
 11  *
 12  * Copyright (c) 1998 Dag Brattli <dagb@cs.uit.no>
 13  * Copyright (c) 1998 Lichen Wang, <lwang@actisys.com>
 14  * Copyright (c) 1998 Actisys Corp., www.actisys.com
 15  * All Rights Reserved
 16  *
 17  * This program is free software; you can redistribute it and/or
 18  * modify it under the terms of the GNU General Public License as
 19  * published by the Free Software Foundation; either version 2 of
 20  * the License, or (at your option) any later version.
 21  *
 22  * Neither Dag Brattli nor University of Tromsø admit liability nor
 23  * provide warranty for any of this software. This material is
 24  * provided "AS-IS" and at no charge.
 25  *
 26  ********************************************************************/
 27
 28 #ifndef PC87108_H
 29 #define PC87108_H
 30
 31 #include <asm/io.h>
 32
 33 /* Flags for configuration register CRF0 */
 34 #define APEDCRC 0x02
 35 #define ENBNKSEL 0x01
 36
 37 /* Set 0 */
 38 #define TXD 0x00/* Transmit data port */
 39 #define RXD 0x00/* Receive data port */
 40
 41 /* Register 1 */
 42 #define IER 0x01/* Interrupt Enable Register*/
 43 #define IER_RXHDL_IE 0x01/* Receiver high data level interrupt */
 44 #define IER_TXLDL_IE 0x02/* Transeiver low data level interrupt */
 45 #define IER_LS_IE 0x04//* Link Status Interrupt */
 46 #define IER_ETXURI 0x04/* Tx underrun */
 47 #define IER_DMA_IE 0x10/* DMA finished interrupt */
 48 #define IER_TXEMP_IE 0x20
 49 #define IER_SFIF_IE 0x40/* Frame status FIFO intr */
 50 #define IER_TMR_IE 0x80/* Timer event */
 51
 52 #define FCR 0x02/* (write only) */
 53 #define FCR_FIFO_EN 0x01/* Enable FIFO's */
 54 #define FCR_RXSR 0x02/* Rx FIFO soft reset */
 55 #define FCR_TXSR 0x04/* Tx FIFO soft reset */
 56 #define FCR_RXTH 0x80/* Rx FIFO threshold (set to 16) */
 57 #define FCR_TXTH 0x20/* Tx FIFO threshold (set to 17) */
 58
 59 #define EIR 0x02/* (read only) */
 60 #define EIR_RXHDL_EV 0x01
 61 #define EIR_TXLDL_EV 0x02
 62 #define EIR_LS_EV 0x04
 63 #define EIR_DMA_EV 0x10
 64 #define EIR_TXEMP_EV 0x20
 65 #define EIR_SFIF_EV 0x40
 66 #define EIR_TMR_EV 0x80
 67
 68 #define LCR 0x03/* Link control register */
 69 #define LCR_WLS_8 0x03/* 8 bits */
 70
 71 #define BSR 0x03/* Bank select register */
 72 #define BSR_BKSE 0x80
 73 #define BANK0 LCR_WLS_8/* Must make sure that we set 8N1 */
 74 #define BANK1 0x80
 75 #define BANK2 0xe0
 76 #define BANK3 0xe4
 77 #define BANK4 0xe8
 78 #define BANK5 0xec
 79 #define BANK6 0xf0
 80 #define BANK7 0xf4
 81
 82 #define MCR 0x04/* Mode Control Register */
 83 #define MCR_MODE_MASK ~(0xd0)
 84 #define MCR_UART 0x00
 85 #define MCR_RESERVED 0x20
 86 #define MCR_SHARP_IR 0x40
 87 #define MCR_SIR 0x60
 88 #define MCR_MIR 0x80
 89 #define MCR_FIR 0xa0
 90 #define MCR_CEIR 0xb0
 91 #define MCR_DMA_EN 0x04
 92 #define MCR_EN_IRQ 0x08
 93 #define MCR_TX_DFR 0x08
 94
 95 #define LSR 0x05/* Link status register */
 96 #define LSR_RXDA 0x01/* Receiver data available */
 97 #define LSR_TXRDY 0x20/* Transmitter ready */
 98 #define LSR_TXEMP 0x40/* Transmitter empty */
 99
 100 #define ASCR 0x07/* Auxillary Status and Control Register */
 101 #define ASCR_RXF_TOUT 0x01/* Rx FIFO timeout */
 102 #define ASCR_FEND_INF 0x02/* Frame end bytes in rx FIFO */
 103 #define ASCR_S_EOT 0x04/* Set end of transmission */
 104 #define ASCT_RXBSY 0x20/* Rx busy */
 105 #define ASCR_TXUR 0x40/* Transeiver underrun */
 106 #define ASCR_CTE 0x80/* Clear timer event */
 107
 108 /* Bank 2 */
 109 #define BGDL 0x00/* Baud Generator Divisor Port (Low Byte) */
 110 #define BGDH 0x01/* Baud Generator Divisor Port (High Byte) */
 111
 112 #define ECR1 0x02/* Extended Control Register 1 */
 113 #define ECR1_EXT_SL 0x01/* Extended Mode Select */
 114 #define ECR1_DMANF 0x02/* DMA Fairness */
 115 #define ECR1_DMATH 0x04
 116 #define ECR1_DMASWP 0x08/* DMA Swap */
 117
 118 #define EXCR2 0x04
 119 #define EXCR2_TFSIZ 0x01/* Rx FIFO size = 32 */
 120 #define EXCR2_RFSIZ 0x04/* Tx FIFO size = 32 */
 121
 122 #define TXFLV 0x06/* Tx FIFO level */
 123 #define RXFLV 0x07/* Rx FIFO level */
 124
 125 /* Bank 3 */
 126 #define MID 0x00
 127
 128 /* Bank 4 */
 129 #define TMRL 0x00/* Timer low byte */
 130 #define TMRH 0x01/* Timer high byte */
 131 #define IRCR1 0x02/* Infrared control register 1 */
 132 #define IRCR1_TMR_EN 0x01/* Timer enable */
 133
 134 #define TFRLL 0x04
 135 #define TFRLH 0x05
 136 #define RFRLL 0x06
 137 #define RFRLH 0x07
 138
 139 /* Bank 5 */
 140 #define IRCR2 0x04/* Infrared control register 2 */
 141 #define IRCR2_MDRS 0x04/* MIR data rate select */
 142 #define IRCR2_FEND_MD 0x20/* */
 143
 144 #define FRM_ST 0x05/* Frame status FIFO */
 145 #define FRM_ST_VLD 0x80/* Frame status FIFO data valid */
 146 #define FRM_ST_ERR_MSK 0x5f
 147 #define FRM_ST_LOST_FR 0x40/* Frame lost */
 148 #define FRM_ST_MAX_LEN 0x10/* Max frame len exceeded */
 149 #define FRM_ST_PHY_ERR 0x08/* Physical layer error */
 150 #define FRM_ST_BAD_CRC 0x04
 151 #define FRM_ST_OVR1 0x02/* Receive overrun */
 152 #define FRM_ST_OVR2 0x01/* Frame status FIFO overrun */
 153
 154 #define RFLFL 0x06
 155 #define RFLFH 0x07
 156
 157 /* Bank 6 */
 158 #define IR_CFG2 0x00
 159 #define IR_CFG2_DIS_CRC 0x02
 160
 161 /* Bank 7 */
 162 #define IRM_CR 0x07/* Infrared module control register */
 163 #define IRM_CR_IRX_MSL 0x40
 164 #define IRM_CR_AF_MNT 0x80/* Automatic format */
 165
 166 /* For storing entries in the status FIFO */
 167 struct st_fifo_entry {
 168 int status;
 169 int len;
 170 };
 171
 172 struct st_fifo {
 173 struct st_fifo_entry entries[10];
 174 int head;
 175 int tail;
 176 int len;
 177 };
 178
 179 /* Private data for each instance */
 180 struct pc87108 {
 181 struct st_fifo st_fifo;
 182
 183 int tx_buff_offsets[10];/* Offsets between frames in tx_buff */
 184 int tx_len;/* Number of frames in tx_buff */
 185
 186 struct irda_device idev;
 187 };
 188
 189 staticinlinevoidswitch_bank(int iobase,int bank)
 190 {
 191 outb( bank, iobase+BSR);
 192 }
 193
 194 #endif