include/asm-sparc64/psrcompat.h

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 1 /* $Id: psrcompat.h,v 1.5 1998/10/06 09:28:39 jj Exp $ */
 2 #ifndef _SPARC64_PSRCOMPAT_H
 3 #define _SPARC64_PSRCOMPAT_H
 4
 5 #include <asm/pstate.h>
 6
 7 /* Old 32-bit PSR fields for the compatability conversion code. */
 8 #define PSR_CWP 0x0000001f/* current window pointer */
 9 #define PSR_ET 0x00000020/* enable traps field */
 10 #define PSR_PS 0x00000040/* previous privilege level */
 11 #define PSR_S 0x00000080/* current privilege level */
 12 #define PSR_PIL 0x00000f00/* processor interrupt level */
 13 #define PSR_EF 0x00001000/* enable floating point */
 14 #define PSR_EC 0x00002000/* enable co-processor */
 15 #define PSR_LE 0x00008000/* SuperSparcII little-endian */
 16 #define PSR_ICC 0x00f00000/* integer condition codes */
 17 #define PSR_C 0x00100000/* carry bit */
 18 #define PSR_V 0x00200000/* overflow bit */
 19 #define PSR_Z 0x00400000/* zero bit */
 20 #define PSR_N 0x00800000/* negative bit */
 21 #define PSR_VERS 0x0f000000/* cpu-version field */
 22 #define PSR_IMPL 0xf0000000/* cpu-implementation field */
 23
 24 #define PSR_V8PLUS 0xff000000/* fake impl/ver, meaning a 64bit CPU is present */
 25 #define PSR_XCC 0x000f0000/* if PSR_V8PLUS, this is %xcc */
 26
 27 extern inlineunsigned inttstate_to_psr(unsigned long tstate)
 28 {
 29 return((tstate & TSTATE_CWP) |
 30  PSR_S |
 31 ((tstate & TSTATE_ICC) >>12) |
 32 ((tstate & TSTATE_XCC) >>20) |
 33  PSR_V8PLUS);
 34 }
 35
 36 extern inlineunsigned longpsr_to_tstate_icc(unsigned int psr)
 37 {
 38 unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) <<12;
 39 if((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS)
 40  tstate |= ((unsigned long)(psr & PSR_XCC)) <<20;
 41 return tstate;
 42 }
 43
 44 #endif/* !(_SPARC64_PSRCOMPAT_H) */