include/asm-mips/stackframe.h

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 1 /*
 2  * include/asm-mips/stackframe.h
 3  *
 4  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Paul M. Antoine.
 5  *
 6  * $Id: stackframe.h,v 1.7 1998/04/28 19:39:15 ralf Exp $
 7  */
 8 #ifndef __ASM_MIPS_STACKFRAME_H
 9 #define __ASM_MIPS_STACKFRAME_H
 10
 11 #include <asm/asm.h>
 12 #include <asm/offset.h>
 13
 14 #define SAVE_AT \
 15  sw $1, PT_R1(sp)
 16
 17 #define SAVE_TEMP \
 18  mfhi v1; \
 19  sw $8, PT_R8(sp); \
 20  sw $9, PT_R9(sp); \
 21  sw v1, PT_HI(sp); \
 22  mflo v1; \
 23  sw $10,PT_R10(sp); \
 24  sw $11, PT_R11(sp); \
 25  sw v1, PT_LO(sp); \
 26  sw $12, PT_R12(sp); \
 27  sw $13, PT_R13(sp); \
 28  sw $14, PT_R14(sp); \
 29  sw $15, PT_R15(sp); \
 30  sw $24, PT_R24(sp)
 31
 32 #define SAVE_STATIC \
 33  sw $16, PT_R16(sp); \
 34  sw $17, PT_R17(sp); \
 35  sw $18, PT_R18(sp); \
 36  sw $19, PT_R19(sp); \
 37  sw $20, PT_R20(sp); \
 38  sw $21, PT_R21(sp); \
 39  sw $22, PT_R22(sp); \
 40  sw $23, PT_R23(sp); \
 41  sw $30, PT_R30(sp)
 42
 43 #define __str2(x) #x
 44 #define __str(x) __str2(x)
 45
 46 #define save_static(frame) \
 47  __asm__ __volatile__( \
 48 "sw\t$16,"__str(PT_R16)"(%0)\n\t" \
 49 "sw\t$17,"__str(PT_R17)"(%0)\n\t" \
 50 "sw\t$18,"__str(PT_R18)"(%0)\n\t" \
 51 "sw\t$19,"__str(PT_R19)"(%0)\n\t" \
 52 "sw\t$20,"__str(PT_R20)"(%0)\n\t" \
 53 "sw\t$21,"__str(PT_R21)"(%0)\n\t" \
 54 "sw\t$22,"__str(PT_R22)"(%0)\n\t" \
 55 "sw\t$23,"__str(PT_R23)"(%0)\n\t" \
 56 "sw\t$30,"__str(PT_R30)"(%0)\n\t" \
 57  :/* No outputs */ \
 58  :"r" (frame))
 59
 60 #define SAVE_SOME \
 61  .set push; \
 62  .set reorder; \
 63  mfc0 k0, CP0_STATUS; \
 64  sll k0, 3;/* extract cu0 bit */ \
 65  .set noreorder; \
 66  bltz k0, 8f; \
 67  move k1, sp; \
 68  .set reorder; \
 69 /* Called from user mode, new stack. */ \
 70  lui k1, %hi(kernelsp); \
 71  lw k1, %lo(kernelsp)(k1); \
 72 8: \
 73  move k0, sp; \
 74  subu sp, k1, PT_SIZE; \
 75  sw k0, PT_R29(sp); \
 76  sw $3, PT_R3(sp); \
 77  sw $0, PT_R0(sp); \
 78  mfc0 v1, CP0_STATUS; \
 79  sw $2, PT_R2(sp); \
 80  sw v1, PT_STATUS(sp); \
 81  sw $4, PT_R4(sp); \
 82  mfc0 v1, CP0_CAUSE; \
 83  sw $5, PT_R5(sp); \
 84  sw v1, PT_CAUSE(sp); \
 85  sw $6, PT_R6(sp); \
 86  mfc0 v1, CP0_EPC; \
 87  sw $7, PT_R7(sp); \
 88  sw v1, PT_EPC(sp); \
 89  sw $25, PT_R25(sp); \
 90  sw $28, PT_R28(sp); \
 91  sw $31, PT_R31(sp); \
 92  ori $28, sp, 0x1fff; \
 93  xori $28, 0x1fff; \
 94  .set pop
 95
 96 #define SAVE_ALL \
 97  SAVE_SOME; \
 98  SAVE_AT; \
 99  SAVE_TEMP; \
 100  SAVE_STATIC
 101
 102 #define RESTORE_AT \
 103  lw $1, PT_R1(sp); \
 104
 105 #define RESTORE_SP \
 106  lw sp, PT_R29(sp)
 107
 108 #define RESTORE_TEMP \
 109  lw $24, PT_LO(sp); \
 110  lw $8, PT_R8(sp); \
 111  lw $9, PT_R9(sp); \
 112  mtlo $24; \
 113  lw $24, PT_HI(sp); \
 114  lw $10,PT_R10(sp); \
 115  lw $11, PT_R11(sp); \
 116  mthi $24; \
 117  lw $12, PT_R12(sp); \
 118  lw $13, PT_R13(sp); \
 119  lw $14, PT_R14(sp); \
 120  lw $15, PT_R15(sp); \
 121  lw $24, PT_R24(sp)
 122
 123 #define RESTORE_STATIC \
 124  lw $16, PT_R16(sp); \
 125  lw $17, PT_R17(sp); \
 126  lw $18, PT_R18(sp); \
 127  lw $19, PT_R19(sp); \
 128  lw $20, PT_R20(sp); \
 129  lw $21, PT_R21(sp); \
 130  lw $22, PT_R22(sp); \
 131  lw $23, PT_R23(sp); \
 132  lw $30, PT_R30(sp)
 133
 134 #define RESTORE_SOME \
 135  .set push; \
 136  .set reorder; \
 137  mfc0 t0, CP0_STATUS; \
 138  .set pop; \
 139  ori t0, 0x1f; \
 140  xori t0, 0x1f; \
 141  mtc0 t0, CP0_STATUS; \
 142  li v1, 0xff00; \
 143  and t0, v1; \
 144  lw v0, PT_STATUS(sp); \
 145  nor v1, $0, v1; \
 146  and v0, v1; \
 147  or v0, t0; \
 148  mtc0 v0, CP0_STATUS; \
 149  lw v1, PT_EPC(sp); \
 150  mtc0 v1, CP0_EPC; \
 151  lw $31, PT_R31(sp); \
 152  lw $28, PT_R28(sp); \
 153  lw $25, PT_R25(sp); \
 154  lw $7, PT_R7(sp); \
 155  lw $6, PT_R6(sp); \
 156  lw $5, PT_R5(sp); \
 157  lw $4, PT_R4(sp); \
 158  lw $3, PT_R3(sp); \
 159  lw $2, PT_R2(sp)
 160
 161 #define RESTORE_ALL \
 162  RESTORE_SOME; \
 163  RESTORE_AT; \
 164  RESTORE_TEMP; \
 165  RESTORE_STATIC; \
 166  RESTORE_SP
 167
 168 /*
 169  * Move to kernel mode and disable interrupts.
 170  * Set cp0 enable bit as sign that we're running on the kernel stack
 171  */
 172 #define CLI \
 173  mfc0 t0,CP0_STATUS; \
 174  li t1,ST0_CU0|0x1f; \
 175  or t0,t1; \
 176  xori t0,0x1f; \
 177  mtc0 t0,CP0_STATUS
 178
 179 /*
 180  * Move to kernel mode and enable interrupts.
 181  * Set cp0 enable bit as sign that we're running on the kernel stack
 182  */
 183 #define STI \
 184  mfc0 t0,CP0_STATUS; \
 185  li t1,ST0_CU0|0x1f; \
 186  or t0,t1; \
 187  xori t0,0x1e; \
 188  mtc0 t0,CP0_STATUS
 189
 190 /*
 191  * Just move to kernel mode and leave interrupts as they are.
 192  * Set cp0 enable bit as sign that we're running on the kernel stack
 193  */
 194 #define KMODE \
 195  mfc0 t0,CP0_STATUS; \
 196  li t1,ST0_CU0|0x1e; \
 197  or t0,t1; \
 198  xori t0,0x1e; \
 199  mtc0 t0,CP0_STATUS
 200
 201 #endif/* __ASM_MIPS_STACKFRAME_H */