CompilerWriterInfo.rst

Architecture & Platform Information for Compiler Writers

• Hardware
  • AArch64 & ARM
  • Itanium (ia64)
  • Lanai
  • MIPS
  • PowerPC
    • IBM - Official manuals and docs
    • Embedded PowerPC Processors manuals and docs
    • Other documents, collections, notes
  • AMDGPU
  • RISC-V
  • C-SKY
  • SPARC
  • SystemZ
  • X86
  • XCore
  • Hexagon
  • Other relevant lists
• ABI
  • Linux
  • macOS
  • Windows
• NVPTX
• Miscellaneous Resources

Note

This document is a work-in-progress. Additions and clarifications are welcome.

Hardware

AArch64 & ARM

• ARMv8-A Architecture Reference Manual This document covers both AArch64 and ARM instructions
• ARMv7-A Architecture Reference Manual This has some useful info on what is supported by older architecture versions.
• ARMv7-M Architecture Reference Manual This covers the Thumb2-only microcontrollers
• ARMv6-M Architecture Reference Manual This covers the Thumb1-only microcontrollers
• ARM C Language Extensions
• ARM NEON Intrinsics Reference
• AArch32 ABI Addenda and Errata
• Cortex-A57 Software Optimization Guide
• Run-time ABI for the ARM Architecture This documents the __aeabi_* helper functions.

Itanium (ia64)

• Itanium documentation

Lanai

• Lanai Instruction Set Architecture

MIPS

• MIPS Processor Architecture
• MIPS 64-bit ELF Object File Specification

PowerPC

IBM - Official manuals and docs

• Power Instruction Set Architecture, Version 3.0B
• POWER9 Processor User's Manual
• Power Instruction Set Architecture, Version 2.07B
• POWER8 Processor User's Manual
• Power Instruction Set Architecture, Versions 2.03 through 2.06 (Internet Archive)
• IBM AIX 7.2 POWER Assembly Reference
• IBM AIX/5L for POWER Assembly Reference

Embedded PowerPC Processors manuals and docs

• Book E: Enhanced PowerPC Architecture
• EREF: A Programmer's Reference Manual for Freescale Embedded Processors (EREFRM)
• Signal Processing Engine (SPE) Programming Environments Manual: A Supplement to the EREF
• Variable-Length Encoding (VLE) Programming Environments Manual: A Supplement to the EREF

Other documents, collections, notes

• PowerPC Compiler Writer's Guide
• Intro to PowerPC Architecture
• Various IBM specifications and white papers
• PowerPC ABI documents
• PowerPC64 alignment of long doubles (from GCC)
• Long branch stubs for powerpc64-linux (from binutils)

AMDGPU

Refer to :doc:`AMDGPUUsage` for additional documentation.

RISC-V

• RISC-V User-Level ISA Specification

C-SKY

• C-SKY Architecture User Guide
• C-SKY V2 ABI

SPARC

• SPARC standards
• SPARC V9 ABI
• SPARC V8 ABI

SystemZ

• z/Architecture Principles of Operation (registration required, free sign-up)

X86

• AMD processor manuals
• Intel 64 and IA-32 manuals
• Intel Itanium documentation
• X86 and X86-64 SysV psABI
• Calling conventions for different C++ compilers and operating systems

XCore

• The XMOS XS1 Architecture (ISA)
• The XMOS XS2 Architecture (ISA)
• Tools Development Guide (includes ABI)

Hexagon

• Hexagon Programmer's Reference Manuals and Hexagon ABI Specification (registration required, free sign-up)

Other relevant lists

• GCC reading list

ABI

• System V Application Binary Interface
• Itanium C++ ABI (This is used for all non-Windows targets.)

Linux

• Linux extensions to gabi
• 64-Bit ELF V2 ABI Specification: Power Architecture
• OpenPOWER ELFv2 Errata: ELFv2 ABI Version 1.4
• PowerPC 64-bit ELF ABI Supplement
• Procedure Call Standard for the AArch64 Architecture
• Procedure Call Standard for the ARM Architecture
• ELF for the ARM Architecture
• ELF for the ARM 64-bit Architecture (AArch64)
• System z ELF ABI Supplement

macOS

• Mach-O Runtime Architecture
• Notes on Mach-O ABI
• ARM64 Function Calling Conventions

Windows

• Microsoft PE/COFF Specification
• ARM64 exception handling
• ARM exception handling
• Overview of ARM64 ABI conventions
• Overview of ARM32 ABI Conventions

NVPTX

• CUDA Documentation includes the PTX ISA and Driver API documentation

Miscellaneous Resources

• Executable File Format library
• GCC prefetch project page has a good survey of the prefetching capabilities of a variety of modern processors.