forked from llvm/llvm-project
- Notifications
You must be signed in to change notification settings - Fork 339
/
Copy pathamdgcn-atomic.ll
424 lines (316 loc) · 25.8 KB
/
amdgcn-atomic.ll
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
; RUN: llvm-as < %s | llvm-dis | FileCheck %s
definevoid@atomic_inc(ptr%ptr0, ptraddrspace(1) %ptr1, ptraddrspace(3) %ptr3) {
; CHECK: atomicrmw uinc_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result0 = calli32@llvm.amdgcn.atomic.inc.i32.p0(ptr%ptr0, i3242, i320, i320, i1false)
; CHECK: atomicrmw uinc_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result1 = calli32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) %ptr1, i3243, i320, i320, i1false)
; CHECK: atomicrmw uinc_wrap ptr addrspace(3) %ptr3, i32 46 syncscope("agent") seq_cst, align 4{{$}}
%result2 = calli32@llvm.amdgcn.atomic.inc.i32.p3(ptraddrspace(3) %ptr3, i3246, i320, i320, i1false)
; CHECK: atomicrmw uinc_wrap ptr %ptr0, i64 48 syncscope("agent") seq_cst, align 8
%result3 = calli64@llvm.amdgcn.atomic.inc.i64.p0(ptr%ptr0, i6448, i320, i320, i1false)
; CHECK: atomicrmw uinc_wrap ptr addrspace(1) %ptr1, i64 45 syncscope("agent") seq_cst, align 8
%result4 = calli64@llvm.amdgcn.atomic.inc.i64.p1(ptraddrspace(1) %ptr1, i6445, i320, i320, i1false)
; CHECK: atomicrmw uinc_wrap ptr addrspace(3) %ptr3, i64 4345 syncscope("agent") seq_cst, align 8
%result5 = calli64@llvm.amdgcn.atomic.inc.i64.p3(ptraddrspace(3) %ptr3, i644345, i320, i320, i1false)
; CHECK: atomicrmw volatile uinc_wrap ptr addrspace(3) %ptr3, i64 4345 syncscope("agent") seq_cst, align 8
%result6 = calli64@llvm.amdgcn.atomic.inc.i64.p3(ptraddrspace(3) %ptr3, i644345, i320, i320, i1true)
retvoid
}
definevoid@atomic_dec(ptr%ptr0, ptraddrspace(1) %ptr1, ptraddrspace(3) %ptr3) {
; CHECK: atomicrmw udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result0 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result1 = calli32@llvm.amdgcn.atomic.dec.i32.p1(ptraddrspace(1) %ptr1, i3243, i320, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr addrspace(3) %ptr3, i32 46 syncscope("agent") seq_cst, align 4{{$}}
%result2 = calli32@llvm.amdgcn.atomic.dec.i32.p3(ptraddrspace(3) %ptr3, i3246, i320, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr %ptr0, i64 48 syncscope("agent") seq_cst, align 8
%result3 = calli64@llvm.amdgcn.atomic.dec.i64.p0(ptr%ptr0, i6448, i320, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr addrspace(1) %ptr1, i64 45 syncscope("agent") seq_cst, align 8
%result4 = calli64@llvm.amdgcn.atomic.dec.i64.p1(ptraddrspace(1) %ptr1, i6445, i320, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr addrspace(3) %ptr3, i64 4345 syncscope("agent") seq_cst, align 8
%result5 = calli64@llvm.amdgcn.atomic.dec.i64.p3(ptraddrspace(3) %ptr3, i644345, i320, i320, i1false)
; CHECK: atomicrmw volatile udec_wrap ptr addrspace(3) %ptr3, i64 4345 syncscope("agent") seq_cst, align 8
%result6 = calli64@llvm.amdgcn.atomic.dec.i64.p3(ptraddrspace(3) %ptr3, i644345, i320, i320, i1true)
retvoid
}
; Test some invalid ordering handling
definevoid@ordering(ptr%ptr0, ptraddrspace(1) %ptr1, ptraddrspace(3) %ptr3) {
; CHECK: atomicrmw volatile uinc_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result0 = calli32@llvm.amdgcn.atomic.inc.i32.p0(ptr%ptr0, i3242, i32 -1, i320, i1true)
; CHECK: atomicrmw volatile uinc_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result1 = calli32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) %ptr1, i3243, i320, i320, i1true)
; CHECK: atomicrmw uinc_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result2 = calli32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) %ptr1, i3243, i321, i320, i1false)
; CHECK: atomicrmw volatile uinc_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory !1
%result3 = calli32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) %ptr1, i3243, i322, i320, i1true)
; CHECK: atomicrmw uinc_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result4 = calli32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) %ptr1, i3243, i323, i320, i1false)
; CHECK: atomicrmw volatile udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result5 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i324, i1true)
; CHECK: atomicrmw udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result6 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i325, i1false)
; CHECK: atomicrmw volatile udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result7 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i326, i1true)
; CHECK: atomicrmw udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result8 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i327, i1false)
; CHECK:= atomicrmw volatile udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result9 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i320, i328, i1true)
; CHECK:= atomicrmw volatile udec_wrap ptr addrspace(1) %ptr1, i32 43 syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !1
%result10 = calli32@llvm.amdgcn.atomic.dec.i32.p1(ptraddrspace(1) %ptr1, i3243, i323, i320, i1true)
retvoid
}
definevoid@immarg_violations(ptr%ptr0, i32%val32, i1%val1) {
; CHECK: atomicrmw udec_wrap ptr %ptr0, i32 42 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result0 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i32%val32, i320, i1false)
; CHECK: atomicrmw udec_wrap ptr %ptr0, i32 42 syncscope("agent") monotonic, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result1 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i322, i32%val32, i1false)
; CHECK: atomicrmw volatile udec_wrap ptr %ptr0, i32 42 syncscope("agent") monotonic, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1{{$}}
%result2 = calli32@llvm.amdgcn.atomic.dec.i32.p0(ptr%ptr0, i3242, i322, i320, i1%val1)
retvoid
}
declarei32@llvm.amdgcn.atomic.inc.i32.p1(ptraddrspace(1) nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei32@llvm.amdgcn.atomic.inc.i32.p3(ptraddrspace(3) nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei32@llvm.amdgcn.atomic.inc.i32.p0(ptrnocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.inc.i64.p1(ptraddrspace(1) nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.inc.i64.p3(ptraddrspace(3) nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.inc.i64.p0(ptrnocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
declarei32@llvm.amdgcn.atomic.dec.i32.p1(ptraddrspace(1) nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei32@llvm.amdgcn.atomic.dec.i32.p3(ptraddrspace(3) nocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei32@llvm.amdgcn.atomic.dec.i32.p0(ptrnocapture, i32, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.dec.i64.p1(ptraddrspace(1) nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.dec.i64.p3(ptraddrspace(3) nocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
declarei64@llvm.amdgcn.atomic.dec.i64.p0(ptrnocapture, i64, i32 immarg, i32 immarg, i1 immarg) #0
; ptr, rmw_value, ordering, scope, isVolatile)
declarefloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) nocapture, float, i32 immarg, i32 immarg, i1 immarg)
declaredouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) nocapture, double, i32 immarg, i32 immarg, i1 immarg)
declare <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) nocapture, <2 x half>, i32 immarg, i32 immarg, i1 immarg)
declare <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) nocapture, <2 x i16>)
definefloat@upgrade_amdgcn_ds_fadd_f32(ptraddrspace(3) %ptr, float%val) {
; CHECK: atomicrmw fadd ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) %ptr, float%val, i320, i320, i1false)
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result1 = callfloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) %ptr, float%val, i320, i320, i1true)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result2 = callfloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) %ptr, float%val, i3243, i323, i1false)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, float %val syncscope("agent") acquire, align 4
%result3 = callfloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) %ptr, float%val, i324, i322, i1false)
retfloat%result3
}
; Handle missing type suffix
declarefloat@llvm.amdgcn.ds.fadd(ptraddrspace(3) nocapture, float, i32 immarg, i32 immarg, i1 immarg)
definefloat@upgrade_amdgcn_ds_fadd_f32_no_suffix(ptraddrspace(3) %ptr, float%val) {
; CHECK: atomicrmw fadd ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fadd(ptraddrspace(3) %ptr, float%val, i320, i320, i1false)
retfloat%result0
}
definevoid@immarg_violations_ds_fadd_f32(ptraddrspace(3) %ptr, float%fval, i32%val32, i1%val1) {
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, float %fval syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fadd.f32(ptraddrspace(3) %ptr, float%fval, i32%val32, i32%val32, i1%val1)
retvoid
}
declarefloat@llvm.amdgcn.ds.fadd.f32broken0(i32, float, i32 immarg, i32 immarg, i1 immarg)
; This will just delete the invalid call, which isn't ideal, but these
; cases were never emitted.
; CHECK-LABEL: define void @ds_fadd_f32_invalid_not_ptr(
; CHECK-NEXT: ret void
definevoid@ds_fadd_f32_invalid_not_ptr(i32%ptr, float%fval) {
%result0 = callfloat@llvm.amdgcn.ds.fadd.f32broken0(i32%ptr, float%fval, i320, i320, i1false)
retvoid
}
declarefloat@llvm.amdgcn.ds.fadd.f32broken1(ptraddrspace(3), double, i32 immarg, i32 immarg, i1 immarg)
; CHECK-LABEL: define void @ds_fadd_f32_invalid_misatch(
; CHECK-NEXT: ret void
definevoid@ds_fadd_f32_invalid_misatch(ptraddrspace(3) %ptr, double%fval) {
%result0 = callfloat@llvm.amdgcn.ds.fadd.f32broken1(ptraddrspace(3) %ptr, double%fval, i320, i320, i1false)
retvoid
}
definedouble@upgrade_amdgcn_ds_fadd_f64(ptraddrspace(3) %ptr, double%val) {
; CHECK: atomicrmw fadd ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result0 = calldouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) %ptr, double%val, i320, i320, i1false)
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result1 = calldouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) %ptr, double%val, i320, i320, i1true)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result2 = calldouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) %ptr, double%val, i3243, i323, i1false)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, double %val syncscope("agent") acquire, align 8
%result3 = calldouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) %ptr, double%val, i324, i322, i1false)
retdouble%result3
}
; CHECK-LABEL: @immarg_violations_ds_fadd_f64(
definevoid@immarg_violations_ds_fadd_f64(ptraddrspace(3) %ptr, double%fval, i32%val32, i1%val1) {
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, double %fval syncscope("agent") seq_cst, align 8
%result0 = calldouble@llvm.amdgcn.ds.fadd.f64(ptraddrspace(3) %ptr, double%fval, i32%val32, i32%val32, i1%val1)
retvoid
}
define <2 x half> @upgrade_amdgcn_ds_fadd_v2f16(ptraddrspace(3) %ptr, <2 x half> %val) {
; CHECK: atomicrmw fadd ptr addrspace(3) %ptr, <2 x half> %val syncscope("agent") seq_cst, align 4
%result0 = call <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) %ptr, <2 x half> %val, i320, i320, i1false)
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, <2 x half> %val syncscope("agent") seq_cst, align 4
%result1 = call <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) %ptr, <2 x half> %val, i320, i320, i1true)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, <2 x half> %val syncscope("agent") seq_cst, align 4
%result2 = call <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) %ptr, <2 x half> %val, i3243, i323, i1false)
; CHECK: = atomicrmw fadd ptr addrspace(3) %ptr, <2 x half> %val syncscope("agent") acquire, align 4
%result3 = call <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) %ptr, <2 x half> %val, i324, i322, i1false)
ret <2 x half> %result3
}
definevoid@immarg_violations_ds_fadd_v2f16(ptraddrspace(3) %ptr, <2 x half> %fval, i32%val32, i1%val1) {
; CHECK: = atomicrmw volatile fadd ptr addrspace(3) %ptr, <2 x half> %fval syncscope("agent") seq_cst, align 4
%result0 = call <2 x half> @llvm.amdgcn.ds.fadd.v2f16(ptraddrspace(3) %ptr, <2 x half> %fval, i32%val32, i32%val32, i1%val1)
retvoid
}
define <2 x i16> @upgrade_amdgcn_ds_fadd_v2bf16__as_i16(ptraddrspace(3) %ptr, <2 x i16> %val) {
; CHECK: [[BC0:%[0-9]+]] = bitcast <2 x i16> %val to <2 x bfloat>
; CHECK-NEXT: [[RMW0:%[0-9]+]] = atomicrmw fadd ptr addrspace(3) %ptr, <2 x bfloat> [[BC0]] syncscope("agent") seq_cst, align 4
; CHECK-NEXT: = bitcast <2 x bfloat> [[RMW0]] to <2 x i16>
%result0 = call <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) %ptr, <2 x i16> %val, i320, i320, i1false)
; CHECK: [[BC1:%[0-9]+]] = bitcast <2 x i16> %val to <2 x bfloat>
; CHECK-NEXT: [[RMW1:%[0-9]+]] = atomicrmw volatile fadd ptr addrspace(3) %ptr, <2 x bfloat> [[BC1]] syncscope("agent") seq_cst, align 4
; CHECK-NEXT: = bitcast <2 x bfloat> [[RMW1]] to <2 x i16>
%result1 = call <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) %ptr, <2 x i16> %val, i320, i320, i1true)
; CHECK: [[BC2:%[0-9]+]] = bitcast <2 x i16> %val to <2 x bfloat>
; CHECK-NEXT: [[RMW2:%[0-9]+]] = atomicrmw fadd ptr addrspace(3) %ptr, <2 x bfloat> [[BC2]] syncscope("agent") seq_cst, align 4
; CHECK-NEXT: = bitcast <2 x bfloat> [[RMW2]] to <2 x i16>
%result2 = call <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) %ptr, <2 x i16> %val, i3243, i323, i1false)
; CHECK: [[BC3:%[0-9]+]] = bitcast <2 x i16> %val to <2 x bfloat>
; CHECK-NEXT: [[RMW3:%[0-9]+]] = atomicrmw fadd ptr addrspace(3) %ptr, <2 x bfloat> [[BC3]] syncscope("agent") acquire, align 4
; CHECK-NEXT: = bitcast <2 x bfloat> [[RMW3]] to <2 x i16>
%result3 = call <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) %ptr, <2 x i16> %val, i324, i322, i1false)
ret <2 x i16> %result3
}
; Somehow the bf16 version was defined as a separate intrinsic with missing arguments.
define <2 x i16> @upgrade_amdgcn_ds_fadd_v2bf16__missing_args_as_i16(ptraddrspace(3) %ptr, <2 x i16> %val) {
; CHECK: [[BC0:%[0-9]+]] = bitcast <2 x i16> %val to <2 x bfloat>
; CHECK-NEXT: [[RMW0:%[0-9]+]] = atomicrmw fadd ptr addrspace(3) %ptr, <2 x bfloat> [[BC0]] syncscope("agent") seq_cst, align 4
; CHECK-NEXT: [[BC1:%[0-9]+]] = bitcast <2 x bfloat> [[RMW0]] to <2 x i16>
; CHECK-NEXT: ret <2 x i16> [[BC1]]
%result0 = call <2 x i16> @llvm.amdgcn.ds.fadd.v2bf16(ptraddrspace(3) %ptr, <2 x i16> %val)
ret <2 x i16> %result0
}
declarefloat@llvm.amdgcn.ds.fmin.f32(ptraddrspace(3) nocapture, float, i32 immarg, i32 immarg, i1 immarg)
declaredouble@llvm.amdgcn.ds.fmin.f64(ptraddrspace(3) nocapture, double, i32 immarg, i32 immarg, i1 immarg)
definefloat@upgrade_amdgcn_ds_fmin_f32(ptraddrspace(3) %ptr, float%val) {
; CHECK: atomicrmw fmin ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fmin.f32(ptraddrspace(3) %ptr, float%val, i320, i320, i1false)
; CHECK: = atomicrmw volatile fmin ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result1 = callfloat@llvm.amdgcn.ds.fmin.f32(ptraddrspace(3) %ptr, float%val, i320, i320, i1true)
; CHECK: = atomicrmw fmin ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result2 = callfloat@llvm.amdgcn.ds.fmin.f32(ptraddrspace(3) %ptr, float%val, i3243, i323, i1false)
; CHECK: = atomicrmw fmin ptr addrspace(3) %ptr, float %val syncscope("agent") acquire, align 4
%result3 = callfloat@llvm.amdgcn.ds.fmin.f32(ptraddrspace(3) %ptr, float%val, i324, i322, i1false)
retfloat%result3
}
definedouble@upgrade_amdgcn_ds_fmin_f64(ptraddrspace(3) %ptr, double%val) {
; CHECK: atomicrmw fmin ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result0 = calldouble@llvm.amdgcn.ds.fmin.f64(ptraddrspace(3) %ptr, double%val, i320, i320, i1false)
; CHECK: = atomicrmw volatile fmin ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result1 = calldouble@llvm.amdgcn.ds.fmin.f64(ptraddrspace(3) %ptr, double%val, i320, i320, i1true)
; CHECK: = atomicrmw fmin ptr addrspace(3) %ptr, double %val syncscope("agent") seq_cst, align 8
%result2 = calldouble@llvm.amdgcn.ds.fmin.f64(ptraddrspace(3) %ptr, double%val, i3243, i323, i1false)
; CHECK: = atomicrmw fmin ptr addrspace(3) %ptr, double %val syncscope("agent") acquire, align 8
%result3 = calldouble@llvm.amdgcn.ds.fmin.f64(ptraddrspace(3) %ptr, double%val, i324, i322, i1false)
retdouble%result3
}
declarefloat@llvm.amdgcn.ds.fmin(ptraddrspace(3) nocapture, float, i32 immarg, i32 immarg, i1 immarg)
definefloat@upgrade_amdgcn_ds_fmin_f32_no_suffix(ptraddrspace(3) %ptr, float%val) {
; CHECK: = atomicrmw fmin ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fmin(ptraddrspace(3) %ptr, float%val, i320, i320, i1false)
retfloat%result0
}
declarefloat@llvm.amdgcn.ds.fmax(ptraddrspace(3) nocapture, float, i32 immarg, i32 immarg, i1 immarg)
definefloat@upgrade_amdgcn_ds_fmax_f32_no_suffix(ptraddrspace(3) %ptr, float%val) {
; CHECK: = atomicrmw fmax ptr addrspace(3) %ptr, float %val syncscope("agent") seq_cst, align 4
%result0 = callfloat@llvm.amdgcn.ds.fmax(ptraddrspace(3) %ptr, float%val, i320, i320, i1false)
retfloat%result0
}
declare <2 x i16> @llvm.amdgcn.flat.atomic.fadd.v2bf16.p0(ptr, <2 x i16>)
define <2 x i16> @upgrade_amdgcn_flat_atomic_fadd_v2bf16_p0(ptr%ptr, <2 x i16> %data) {
; CHECK: [[BC0:%.+]] = bitcast <2 x i16> %data to <2 x bfloat>
; CHECK-NEXT: [[ATOMIC:%.+]] = atomicrmw fadd ptr %ptr, <2 x bfloat> [[BC0]] syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
; CHECK-NEXT: [[BC1:%.+]] = bitcast <2 x bfloat> [[ATOMIC]] to <2 x i16>
; CHECK-NEXT: ret <2 x i16> [[BC1]]
%result = call <2 x i16> @llvm.amdgcn.flat.atomic.fadd.v2bf16.p0(ptr%ptr, <2 x i16> %data)
ret <2 x i16> %result
}
declare <2 x i16> @llvm.amdgcn.global.atomic.fadd.v2bf16.p1(ptraddrspace(1), <2 x i16>)
define <2 x i16> @upgrade_amdgcn_global_atomic_fadd_v2bf16_p1(ptraddrspace(1) %ptr, <2 x i16> %data) {
; CHECK: [[BC0:%.+]] = bitcast <2 x i16> %data to <2 x bfloat>
; CHECK-NEXT: [[ATOMIC:%.+]] = atomicrmw fadd ptr addrspace(1) %ptr, <2 x bfloat> [[BC0]] syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
; CHECK-NEXT: [[BC1:%.+]] = bitcast <2 x bfloat> [[ATOMIC]] to <2 x i16>
; CHECK-NEXT: ret <2 x i16> [[BC1]]
%result = call <2 x i16> @llvm.amdgcn.global.atomic.fadd.v2bf16.p1(ptraddrspace(1) %ptr, <2 x i16> %data)
ret <2 x i16> %result
}
declare <2 x half> @llvm.amdgcn.flat.atomic.fadd.v2f16.p0.v2f16(ptrnocapture, <2 x half>) #0
define <2 x half> @upgrade_amdgcn_flat_atomic_fadd_v2f16_p0_v2f16(ptr%ptr, <2 x half> %data) {
; CHECK: %{{.+}} = atomicrmw fadd ptr %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !{{[0-9]+}}, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = call <2 x half> @llvm.amdgcn.flat.atomic.fadd.v2f16.p0.v2f16(ptr%ptr, <2 x half> %data)
ret <2 x half> %result
}
declare <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptraddrspace(1) nocapture, <2 x half>) #0
define <2 x half> @upgrade_amdgcn_global_atomic_fadd_v2f16_p1_v2f16(ptraddrspace(1) %ptr, <2 x half> %data) {
; CHECK: %{{.+}} = atomicrmw fadd ptr addrspace(1) %ptr, <2 x half> %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = call <2 x half> @llvm.amdgcn.global.atomic.fadd.v2f16.p1.v2f16(ptraddrspace(1) %ptr, <2 x half> %data)
ret <2 x half> %result
}
declarefloat@llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptrnocapture, float) #0
definefloat@upgrade_amdgcn_flat_atomic_fadd_f32_p0_f32(ptr%ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fadd ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !{{[0-9]+}}, !amdgpu.no.fine.grained.memory !{{[0-9]+}}, !amdgpu.ignore.denormal.mode !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr%ptr, float%data)
retfloat%result
}
declarefloat@llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptraddrspace(1) nocapture, float) #0
definefloat@upgrade_amdgcn_global_atomic_fadd_f32_p1_f32(ptraddrspace(1) %ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fadd ptr addrspace(1) %ptr, float %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+}}, !amdgpu.ignore.denormal.mode !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.global.atomic.fadd.f32.p1.f32(ptraddrspace(1) %ptr, float%data)
retfloat%result
}
declarefloat@llvm.amdgcn.flat.atomic.fmin.f32.p0.f32(ptrnocapture, float) #0
definefloat@upgrade_amdgcn_flat_atomic_fmin_f32_p0_f32(ptr%ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fmin ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.flat.atomic.fmin.f32.p0.f32(ptr%ptr, float%data)
retfloat%result
}
declarefloat@llvm.amdgcn.global.atomic.fmin.f32.p1.f32(ptraddrspace(1) nocapture, float) #0
definefloat@upgrade_amdgcn_global_atomic_fmin_f32_p1_f32(ptraddrspace(1) %ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fmin ptr addrspace(1) %ptr, float %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.global.atomic.fmin.f32.p1.f32(ptraddrspace(1) %ptr, float%data)
retfloat%result
}
declaredouble@llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptrnocapture, double) #0
definedouble@upgrade_amdgcn_flat_atomic_fmin_f64_p0_f64(ptr%ptr, double%data) {
; CHECK: %{{.+}} = atomicrmw fmin ptr %ptr, double %data syncscope("agent") seq_cst, align 8, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = calldouble@llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptr%ptr, double%data)
retdouble%result
}
declaredouble@llvm.amdgcn.global.atomic.fmin.f64.p1.f64(ptraddrspace(1) nocapture, double) #0
definedouble@upgrade_amdgcn_global_atomic_fmin_f64_p1_f64(ptraddrspace(1) %ptr, double%data) {
; CHECK: %{{.+}} = atomicrmw fmin ptr addrspace(1) %ptr, double %data syncscope("agent") seq_cst, align 8, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = calldouble@llvm.amdgcn.global.atomic.fmin.f64.p1.f64(ptraddrspace(1) %ptr, double%data)
retdouble%result
}
declarefloat@llvm.amdgcn.flat.atomic.fmax.f32.p0.f32(ptrnocapture, float) #0
definefloat@upgrade_amdgcn_flat_atomic_fmax_f32_p0_f32(ptr%ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fmax ptr %ptr, float %data syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.flat.atomic.fmax.f32.p0.f32(ptr%ptr, float%data)
retfloat%result
}
declarefloat@llvm.amdgcn.global.atomic.fmax.f32.p1.f32(ptraddrspace(1) nocapture, float) #0
definefloat@upgrade_amdgcn_global_atomic_fmax_f32_p1_f32(ptraddrspace(1) %ptr, float%data) {
; CHECK: %{{.+}} = atomicrmw fmax ptr addrspace(1) %ptr, float %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = callfloat@llvm.amdgcn.global.atomic.fmax.f32.p1.f32(ptraddrspace(1) %ptr, float%data)
retfloat%result
}
declaredouble@llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptrnocapture, double) #0
definedouble@upgrade_amdgcn_flat_atomic_fmax_f64_p0_f64(ptr%ptr, double%data) {
; CHECK: %{{.+}} = atomicrmw fmax ptr %ptr, double %data syncscope("agent") seq_cst, align 8, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = calldouble@llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptr%ptr, double%data)
retdouble%result
}
declaredouble@llvm.amdgcn.global.atomic.fmax.f64.p1.f64(ptraddrspace(1) nocapture, double) #0
definedouble@upgrade_amdgcn_global_atomic_fmax_f64_p1_f64(ptraddrspace(1) %ptr, double%data) {
; CHECK: %{{.+}} = atomicrmw fmax ptr addrspace(1) %ptr, double %data syncscope("agent") seq_cst, align 8, !amdgpu.no.fine.grained.memory !{{[0-9]+$}}
%result = calldouble@llvm.amdgcn.global.atomic.fmax.f64.p1.f64(ptraddrspace(1) %ptr, double%data)
retdouble%result
}
attributes #0 = { argmemonlynounwind willreturn }
; CHECK: !0 = !{i32 5, i32 6}
; CHECK: !1 = !{}
