hwintrinsicxarch.cpp

// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

#include"jitpch.h"
#include"hwintrinsic.h"

#ifdef FEATURE_HW_INTRINSICS

//------------------------------------------------------------------------
// X64VersionOfIsa: Gets the corresponding 64-bit only InstructionSet for a given InstructionSet
//
// Arguments:
// isa -- The InstructionSet ID
//
// Return Value:
// The 64-bit only InstructionSet associated with isa
static InstructionSet X64VersionOfIsa(InstructionSet isa)
{
switch (isa)
 {
case InstructionSet_SSE:
return InstructionSet_SSE_X64;
case InstructionSet_SSE2:
return InstructionSet_SSE2_X64;
case InstructionSet_SSE41:
return InstructionSet_SSE41_X64;
case InstructionSet_SSE42:
return InstructionSet_SSE42_X64;
case InstructionSet_BMI1:
return InstructionSet_BMI1_X64;
case InstructionSet_BMI2:
return InstructionSet_BMI2_X64;
case InstructionSet_LZCNT:
return InstructionSet_LZCNT_X64;
case InstructionSet_POPCNT:
return InstructionSet_POPCNT_X64;
default:
unreached();
 }
}

//------------------------------------------------------------------------
// lookupInstructionSet: Gets the InstructionSet for a given class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
//
// Return Value:
// The InstructionSet associated with className
static InstructionSet lookupInstructionSet(constchar* className)
{
assert(className != nullptr);
if (className[0] == 'A')
 {
if (strcmp(className, "Aes") == 0)
 {
return InstructionSet_AES;
 }
if (strcmp(className, "Avx") == 0)
 {
return InstructionSet_AVX;
 }
if (strcmp(className, "Avx2") == 0)
 {
return InstructionSet_AVX2;
 }
 }
elseif (className[0] == 'S')
 {
if (strcmp(className, "Sse") == 0)
 {
return InstructionSet_SSE;
 }
if (strcmp(className, "Sse2") == 0)
 {
return InstructionSet_SSE2;
 }
if (strcmp(className, "Sse3") == 0)
 {
return InstructionSet_SSE3;
 }
if (strcmp(className, "Ssse3") == 0)
 {
return InstructionSet_SSSE3;
 }
if (strcmp(className, "Sse41") == 0)
 {
return InstructionSet_SSE41;
 }
if (strcmp(className, "Sse42") == 0)
 {
return InstructionSet_SSE42;
 }
 }
elseif (className[0] == 'B')
 {
if (strcmp(className, "Bmi1") == 0)
 {
return InstructionSet_BMI1;
 }
if (strcmp(className, "Bmi2") == 0)
 {
return InstructionSet_BMI2;
 }
 }
elseif (className[0] == 'P')
 {
if (strcmp(className, "Pclmulqdq") == 0)
 {
return InstructionSet_PCLMULQDQ;
 }
if (strcmp(className, "Popcnt") == 0)
 {
return InstructionSet_POPCNT;
 }
 }
elseif (className[0] == 'V')
 {
if (strncmp(className, "Vector128", 9) == 0)
 {
return InstructionSet_Vector128;
 }
elseif (strncmp(className, "Vector256", 9) == 0)
 {
return InstructionSet_Vector256;
 }
 }
elseif (strcmp(className, "Fma") == 0)
 {
return InstructionSet_FMA;
 }
elseif (strcmp(className, "Lzcnt") == 0)
 {
return InstructionSet_LZCNT;
 }

return InstructionSet_ILLEGAL;
}

//------------------------------------------------------------------------
// lookupIsa: Gets the InstructionSet for a given class name and enclsoing class name
//
// Arguments:
// className -- The name of the class associated with the InstructionSet to lookup
// enclosingClassName -- The name of the enclosing class of X64 classes
//
// Return Value:
// The InstructionSet associated with className and enclosingClassName
InstructionSet HWIntrinsicInfo::lookupIsa(constchar* className, constchar* enclosingClassName)
{
assert(className != nullptr);

if (strcmp(className, "X64") == 0)
 {
assert(enclosingClassName != nullptr);
returnX64VersionOfIsa(lookupInstructionSet(enclosingClassName));
 }
else
 {
returnlookupInstructionSet(className);
 }
}

//------------------------------------------------------------------------
// lookupImmUpperBound: Gets the upper bound for the imm-value of a given NamedIntrinsic
//
// Arguments:
// id -- The NamedIntrinsic associated with the HWIntrinsic to lookup
//
// Return Value:
// The upper bound for the imm-value of the intrinsic associated with id
//
intHWIntrinsicInfo::lookupImmUpperBound(NamedIntrinsic id)
{
assert(HWIntrinsicInfo::lookupCategory(id) == HW_Category_IMM);

switch (id)
 {
case NI_AVX_Compare:
case NI_AVX_CompareScalar:
 {
assert(!HWIntrinsicInfo::HasFullRangeImm(id));
return31; // enum FloatComparisonMode has 32 values
 }

case NI_AVX2_GatherVector128:
case NI_AVX2_GatherVector256:
case NI_AVX2_GatherMaskVector128:
case NI_AVX2_GatherMaskVector256:
return8;

default:
 {
assert(HWIntrinsicInfo::HasFullRangeImm(id));
return255;
 }
 }
}

//------------------------------------------------------------------------
// isInImmRange: Check if ival is valid for the intrinsic
//
// Arguments:
// id -- The NamedIntrinsic associated with the HWIntrinsic to lookup
// ival -- the imm value to be checked
//
// Return Value:
// true if ival is valid for the intrinsic
//
boolHWIntrinsicInfo::isInImmRange(NamedIntrinsic id, int ival)
{
assert(HWIntrinsicInfo::lookupCategory(id) == HW_Category_IMM);

if (isAVX2GatherIntrinsic(id))
 {
return ival == 1 || ival == 2 || ival == 4 || ival == 8;
 }
else
 {
return ival <= lookupImmUpperBound(id) && ival >= 0;
 }
}

//------------------------------------------------------------------------
// isAVX2GatherIntrinsic: Check if the intrinsic is AVX Gather*
//
// Arguments:
// id -- The NamedIntrinsic associated with the HWIntrinsic to lookup
//
// Return Value:
// true if id is AVX Gather* intrinsic
//
boolHWIntrinsicInfo::isAVX2GatherIntrinsic(NamedIntrinsic id)
{
switch (id)
 {
case NI_AVX2_GatherVector128:
case NI_AVX2_GatherVector256:
case NI_AVX2_GatherMaskVector128:
case NI_AVX2_GatherMaskVector256:
returntrue;
default:
returnfalse;
 }
}

//------------------------------------------------------------------------
// isFullyImplementedIsa: Gets a value that indicates whether the InstructionSet is fully implemented
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is supported; otherwise, false
boolHWIntrinsicInfo::isFullyImplementedIsa(InstructionSet isa)
{
switch (isa)
 {
// These ISAs are fully implemented
case InstructionSet_AES:
case InstructionSet_AVX:
case InstructionSet_AVX2:
case InstructionSet_BMI1:
case InstructionSet_BMI2:
case InstructionSet_BMI1_X64:
case InstructionSet_BMI2_X64:
case InstructionSet_FMA:
case InstructionSet_LZCNT:
case InstructionSet_LZCNT_X64:
case InstructionSet_PCLMULQDQ:
case InstructionSet_POPCNT:
case InstructionSet_POPCNT_X64:
case InstructionSet_SSE:
case InstructionSet_SSE_X64:
case InstructionSet_SSE2:
case InstructionSet_SSE2_X64:
case InstructionSet_SSE3:
case InstructionSet_SSSE3:
case InstructionSet_SSE41:
case InstructionSet_SSE41_X64:
case InstructionSet_SSE42:
case InstructionSet_SSE42_X64:
case InstructionSet_Vector128:
case InstructionSet_Vector256:
 {
returntrue;
 }

default:
 {
unreached();
 }
 }
}

//------------------------------------------------------------------------
// isScalarIsa: Gets a value that indicates whether the InstructionSet is scalar
//
// Arguments:
// isa - The InstructionSet to check
//
// Return Value:
// true if isa is scalar; otherwise, false
boolHWIntrinsicInfo::isScalarIsa(InstructionSet isa)
{
switch (isa)
 {
case InstructionSet_BMI1:
case InstructionSet_BMI2:
case InstructionSet_BMI1_X64:
case InstructionSet_BMI2_X64:
case InstructionSet_LZCNT:
case InstructionSet_LZCNT_X64:
case InstructionSet_POPCNT:
case InstructionSet_POPCNT_X64:
 {
returntrue;
 }

default:
 {
returnfalse;
 }
 }
}

//------------------------------------------------------------------------
// impNonConstFallback: convert certain SSE2/AVX2 shift intrinsic to its semantic alternative when the imm-arg is
// not a compile-time constant
//
// Arguments:
// intrinsic -- intrinsic ID
// simdType -- Vector type
// baseType -- base type of the Vector128/256<T>
//
// Return Value:
// return the IR of semantic alternative on non-const imm-arg
//
GenTree* Compiler::impNonConstFallback(NamedIntrinsic intrinsic, var_types simdType, var_types baseType)
{
assert(HWIntrinsicInfo::NoJmpTableImm(intrinsic));
switch (intrinsic)
 {
case NI_SSE2_ShiftLeftLogical:
case NI_SSE2_ShiftRightArithmetic:
case NI_SSE2_ShiftRightLogical:
case NI_AVX2_ShiftLeftLogical:
case NI_AVX2_ShiftRightArithmetic:
case NI_AVX2_ShiftRightLogical:
 {
 GenTree* op2 = impPopStack().val;
 GenTree* op1 = impSIMDPopStack(simdType);
 GenTree* tmpOp =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, op2, NI_SSE2_ConvertScalarToVector128Int32, TYP_INT, 16);
returngtNewSimdHWIntrinsicNode(simdType, op1, tmpOp, intrinsic, baseType, genTypeSize(simdType));
 }

default:
unreached();
 }
}

//------------------------------------------------------------------------
// impSpecialIntrinsic: dispatch intrinsics to their own implementation
//
// Arguments:
// intrinsic -- id of the intrinsic function.
// method -- method handle of the intrinsic function.
// sig -- signature of the intrinsic call
// mustExpand -- true if the compiler is compiling the fallback(GT_CALL) of this intrinsics
//
// Return Value:
// the expanded intrinsic.
//
GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
 CORINFO_CLASS_HANDLE clsHnd,
 CORINFO_METHOD_HANDLE method,
 CORINFO_SIG_INFO* sig,
bool mustExpand)
{
// other intrinsics need special importation
switch (HWIntrinsicInfo::lookupIsa(intrinsic))
 {
case InstructionSet_Vector128:
case InstructionSet_Vector256:
returnimpBaseIntrinsic(intrinsic, clsHnd, method, sig, mustExpand);
case InstructionSet_SSE:
returnimpSSEIntrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_SSE2:
returnimpSSE2Intrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_SSE42:
case InstructionSet_SSE42_X64:
returnimpSSE42Intrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_AVX:
case InstructionSet_AVX2:
returnimpAvxOrAvx2Intrinsic(intrinsic, method, sig, mustExpand);

case InstructionSet_AES:
returnimpAESIntrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_BMI1:
case InstructionSet_BMI1_X64:
case InstructionSet_BMI2:
case InstructionSet_BMI2_X64:
returnimpBMI1OrBMI2Intrinsic(intrinsic, method, sig, mustExpand);

case InstructionSet_FMA:
returnimpFMAIntrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_LZCNT:
case InstructionSet_LZCNT_X64:
returnimpLZCNTIntrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_PCLMULQDQ:
returnimpPCLMULQDQIntrinsic(intrinsic, method, sig, mustExpand);
case InstructionSet_POPCNT:
case InstructionSet_POPCNT_X64:
returnimpPOPCNTIntrinsic(intrinsic, method, sig, mustExpand);
default:
unreached();
 }
}

//------------------------------------------------------------------------
// impBaseIntrinsic: dispatch intrinsics to their own implementation
//
// Arguments:
// intrinsic -- id of the intrinsic function.
// method -- method handle of the intrinsic function.
// sig -- signature of the intrinsic call
// mustExpand -- true if the compiler is compiling the fallback(GT_CALL) of this intrinsics
//
// Return Value:
// the expanded intrinsic.
//
GenTree* Compiler::impBaseIntrinsic(NamedIntrinsic intrinsic,
 CORINFO_CLASS_HANDLE clsHnd,
 CORINFO_METHOD_HANDLE method,
 CORINFO_SIG_INFO* sig,
bool mustExpand)
{
 GenTree* retNode = nullptr;
 GenTree* op1 = nullptr;

if (!featureSIMD)
 {
returnnullptr;
 }

unsigned simdSize = 0;
 var_types baseType = TYP_UNKNOWN;
 var_types retType = JITtype2varType(sig->retType);

assert(!sig->hasThis());

if (HWIntrinsicInfo::BaseTypeFromFirstArg(intrinsic))
 {
 baseType = getBaseTypeAndSizeOfSIMDType(info.compCompHnd->getArgClass(sig, sig->args), &simdSize);

if (retType == TYP_STRUCT)
 {
unsigned retSimdSize = 0;
 var_types retBasetype = getBaseTypeAndSizeOfSIMDType(sig->retTypeClass, &retSimdSize);
if (!varTypeIsArithmetic(retBasetype))
 {
returnnullptr;
 }
 retType = getSIMDTypeForSize(retSimdSize);
 }
 }
elseif (retType == TYP_STRUCT)
 {
 baseType = getBaseTypeAndSizeOfSIMDType(sig->retTypeClass, &simdSize);
 retType = getSIMDTypeForSize(simdSize);
 }
else
 {
 baseType = getBaseTypeAndSizeOfSIMDType(clsHnd, &simdSize);
 }

if (!varTypeIsArithmetic(baseType))
 {
returnnullptr;
 }

switch (intrinsic)
 {
case NI_Vector256_As:
case NI_Vector256_AsByte:
case NI_Vector256_AsDouble:
case NI_Vector256_AsInt16:
case NI_Vector256_AsInt32:
case NI_Vector256_AsInt64:
case NI_Vector256_AsSByte:
case NI_Vector256_AsSingle:
case NI_Vector256_AsUInt16:
case NI_Vector256_AsUInt32:
case NI_Vector256_AsUInt64:
 {
if (!compSupports(InstructionSet_AVX))
 {
// We don't want to deal with TYP_SIMD32 if the compiler doesn't otherwise support the type.
break;
 }

 __fallthrough;
 }

case NI_Vector128_As:
case NI_Vector128_AsByte:
case NI_Vector128_AsDouble:
case NI_Vector128_AsInt16:
case NI_Vector128_AsInt32:
case NI_Vector128_AsInt64:
case NI_Vector128_AsSByte:
case NI_Vector128_AsSingle:
case NI_Vector128_AsUInt16:
case NI_Vector128_AsUInt32:
case NI_Vector128_AsUInt64:
 {
// We fold away the cast here, as it only exists to satisfy
// the type system. It is safe to do this here since the retNode type
// and the signature return type are both the same TYP_SIMD.

assert(sig->numArgs == 1);

 retNode = impSIMDPopStack(retType, /* expectAddr: */false, sig->retTypeClass);
SetOpLclRelatedToSIMDIntrinsic(retNode);
assert(retNode->gtType == getSIMDTypeForSize(getSIMDTypeSizeInBytes(sig->retTypeSigClass)));
break;
 }

case NI_Vector128_Count:
case NI_Vector256_Count:
 {
assert(sig->numArgs == 0);

 GenTreeIntCon* countNode = gtNewIconNode(getSIMDVectorLength(simdSize, baseType), TYP_INT);
 countNode->gtFlags |= GTF_ICON_SIMD_COUNT;
 retNode = countNode;
break;
 }

case NI_Vector128_CreateScalarUnsafe:
 {
assert(sig->numArgs == 1);

#ifdef _TARGET_X86_
if (varTypeIsLong(baseType))
 {
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
 }
#endif// _TARGET_X86_

if (compSupports(InstructionSet_SSE2) || (compSupports(InstructionSet_SSE) && (baseType == TYP_FLOAT)))
 {
 op1 = impPopStack().val;
 retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, baseType, simdSize);
 }
break;
 }

case NI_Vector128_ToScalar:
 {
assert(sig->numArgs == 1);

if (compSupports(InstructionSet_SSE) && varTypeIsFloating(baseType))
 {
 op1 = impSIMDPopStack(getSIMDTypeForSize(simdSize));
 retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, baseType, 16);
 }
break;
 }

case NI_Vector128_ToVector256:
case NI_Vector128_ToVector256Unsafe:
case NI_Vector256_GetLower:
 {
assert(sig->numArgs == 1);

if (compSupports(InstructionSet_AVX))
 {
 op1 = impSIMDPopStack(getSIMDTypeForSize(simdSize));
 retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, baseType, simdSize);
 }
break;
 }

case NI_Vector128_Zero:
 {
assert(sig->numArgs == 0);

if (compSupports(InstructionSet_SSE))
 {
 retNode = gtNewSimdHWIntrinsicNode(retType, intrinsic, baseType, simdSize);
 }
break;
 }

case NI_Vector256_CreateScalarUnsafe:
 {
assert(sig->numArgs == 1);

#ifdef _TARGET_X86_
if (varTypeIsLong(baseType))
 {
// TODO-XARCH-CQ: It may be beneficial to emit the movq
// instruction, which takes a 64-bit memory address and
// works on 32-bit x86 systems.
break;
 }
#endif// _TARGET_X86_

if (compSupports(InstructionSet_AVX))
 {
 op1 = impPopStack().val;
 retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, baseType, simdSize);
 }
break;
 }

case NI_Vector256_ToScalar:
 {
assert(sig->numArgs == 1);

if (compSupports(InstructionSet_AVX) && varTypeIsFloating(baseType))
 {
 op1 = impSIMDPopStack(getSIMDTypeForSize(simdSize));
 retNode = gtNewSimdHWIntrinsicNode(retType, op1, intrinsic, baseType, 32);
 }
break;
 }

case NI_Vector256_Zero:
 {
assert(sig->numArgs == 0);

if (compSupports(InstructionSet_AVX))
 {
 retNode = gtNewSimdHWIntrinsicNode(retType, intrinsic, baseType, simdSize);
 }
break;
 }

case NI_Vector256_WithElement:
 {
if (!compSupports(InstructionSet_AVX))
 {
// Using software fallback if JIT/hardware don't support AVX instructions and YMM registers
returnnullptr;
 }
 __fallthrough;
 }

case NI_Vector128_WithElement:
 {
assert(sig->numArgs == 3);
 GenTree* indexOp = impStackTop(1).val;
if (!compSupports(InstructionSet_SSE2) || !varTypeIsArithmetic(baseType) || !indexOp->OperIsConst())
 {
// Using software fallback if
// 1. JIT/hardware don't support SSE2 instructions
// 2. baseType is not a numeric type (throw execptions)
// 3. index is not a constant
returnnullptr;
 }

switch (baseType)
 {
// Using software fallback if baseType is not supported by hardware
case TYP_BYTE:
case TYP_UBYTE:
case TYP_INT:
case TYP_UINT:
if (!compSupports(InstructionSet_SSE41))
 {
returnnullptr;
 }
break;

case TYP_LONG:
case TYP_ULONG:
if (!compSupports(InstructionSet_SSE41_X64))
 {
returnnullptr;
 }
break;

case TYP_DOUBLE:
case TYP_FLOAT:
case TYP_SHORT:
case TYP_USHORT:
// short/ushort/float/double is supported by SSE2
break;

default:
unreached();
break;
 }

ssize_t imm8 = indexOp->AsIntCon()->IconValue();
ssize_t cachedImm8 = imm8;
ssize_t count = simdSize / genTypeSize(baseType);

if (imm8 >= count || imm8 < 0)
 {
// Using software fallback if index is out of range (throw exeception)
returnnullptr;
 }

 GenTree* valueOp = impPopStack().val;
impPopStack();
 GenTree* vectorOp = impSIMDPopStack(getSIMDTypeForSize(simdSize));

 GenTree* clonedVectorOp = nullptr;

if (simdSize == 32)
 {
// Extract the half vector that will be modified
assert(compSupports(InstructionSet_AVX));

// copy `vectorOp` to accept the modified half vector
 vectorOp = impCloneExpr(vectorOp, &clonedVectorOp, NO_CLASS_HANDLE, (unsigned)CHECK_SPILL_ALL,
nullptrDEBUGARG("Clone Vector for Vector256<T>.WithElement"));

if (imm8 >= count / 2)
 {
 imm8 -= count / 2;
 vectorOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, gtNewIconNode(1), NI_AVX_ExtractVector128,
 baseType, simdSize);
 }
else
 {
 vectorOp =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, NI_Vector256_GetLower, baseType, simdSize);
 }
 }

 GenTree* immNode = gtNewIconNode(imm8);

switch (baseType)
 {
case TYP_LONG:
case TYP_ULONG:
 retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, valueOp, immNode, NI_SSE41_X64_Insert,
 baseType, 16);
break;

case TYP_FLOAT:
 {
if (!compSupports(InstructionSet_SSE41))
 {
// Emulate Vector128<float>.WithElement by SSE instructions
if (imm8 == 0)
 {
// vector.WithElement(0, value)
// =>
// movss xmm0, xmm1 (xmm0 = vector, xmm1 = value)
 valueOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp, NI_Vector128_CreateScalarUnsafe,
 TYP_FLOAT, 16);
 retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, valueOp, NI_SSE_MoveScalar,
 TYP_FLOAT, 16);
 }
elseif (imm8 == 1)
 {
// vector.WithElement(1, value)
// =>
// shufps xmm1, xmm0, 0 (xmm0 = vector, xmm1 = value)
// shufps xmm1, xmm0, 226
 GenTree* tmpOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp,
 NI_Vector128_CreateScalarUnsafe, TYP_FLOAT, 16);
 GenTree* dupVectorOp = nullptr;
 vectorOp = impCloneExpr(vectorOp, &dupVectorOp, NO_CLASS_HANDLE, (unsigned)CHECK_SPILL_ALL,
nullptrDEBUGARG("Clone Vector for Vector128<float>.WithElement"));
 tmpOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmpOp, vectorOp, gtNewIconNode(0),
 NI_SSE_Shuffle, TYP_FLOAT, 16);
 retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD16, tmpOp, dupVectorOp, gtNewIconNode(226),
 NI_SSE_Shuffle, TYP_FLOAT, 16);
 }
else
 {
ssize_t controlBits1 = 0;
ssize_t controlBits2 = 0;
if (imm8 == 2)
 {
 controlBits1 = 48;
 controlBits2 = 132;
 }
else
 {
 controlBits1 = 32;
 controlBits2 = 36;
 }
// vector.WithElement(2, value)
// =>
// shufps xmm1, xmm0, 48 (xmm0 = vector, xmm1 = value)
// shufps xmm0, xmm1, 132
//
// vector.WithElement(3, value)
// =>
// shufps xmm1, xmm0, 32 (xmm0 = vector, xmm1 = value)
// shufps xmm0, xmm1, 36
 GenTree* tmpOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp,
 NI_Vector128_CreateScalarUnsafe, TYP_FLOAT, 16);
 GenTree* dupVectorOp = nullptr;
 vectorOp = impCloneExpr(vectorOp, &dupVectorOp, NO_CLASS_HANDLE, (unsigned)CHECK_SPILL_ALL,
nullptrDEBUGARG("Clone Vector for Vector128<float>.WithElement"));
 valueOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, tmpOp, gtNewIconNode(controlBits1),
 NI_SSE_Shuffle, TYP_FLOAT, 16);
 retNode =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp, dupVectorOp, gtNewIconNode(controlBits2),
 NI_SSE_Shuffle, TYP_FLOAT, 16);
 }
break;
 }
else
 {
 valueOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp, NI_Vector128_CreateScalarUnsafe,
 TYP_FLOAT, 16);
 immNode->AsIntCon()->SetIconValue(imm8 * 16);
 __fallthrough;
 }
 }

case TYP_BYTE:
case TYP_UBYTE:
case TYP_INT:
case TYP_UINT:
 retNode =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, valueOp, immNode, NI_SSE41_Insert, baseType, 16);
break;

case TYP_SHORT:
case TYP_USHORT:
 retNode =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, valueOp, immNode, NI_SSE2_Insert, baseType, 16);
break;

case TYP_DOUBLE:
 {
// vector.WithElement(0, value)
// =>
// movsd xmm0, xmm1 (xmm0 = vector, xmm1 = value)
//
// vector.WithElement(1, value)
// =>
// unpcklpd xmm0, xmm1 (xmm0 = vector, xmm1 = value)
 valueOp =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, valueOp, NI_Vector128_CreateScalarUnsafe, TYP_DOUBLE, 16);
 NamedIntrinsic in = (imm8 == 0) ? NI_SSE2_MoveScalar : NI_SSE2_UnpackLow;
 retNode = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, valueOp, in, TYP_DOUBLE, 16);
break;
 }

default:
unreached();
break;
 }

if (simdSize == 32)
 {
assert(clonedVectorOp);
int upperOrLower = (cachedImm8 >= count / 2) ? 1 : 0;
 retNode = gtNewSimdHWIntrinsicNode(retType, clonedVectorOp, retNode, gtNewIconNode(upperOrLower),
 NI_AVX_InsertVector128, baseType, simdSize);
 }

break;
 }

case NI_Vector256_GetElement:
 {
if (!compSupports(InstructionSet_AVX))
 {
// Using software fallback if JIT/hardware don't support AVX instructions and YMM registers
returnnullptr;
 }
 __fallthrough;
 }

case NI_Vector128_GetElement:
 {
assert(sig->numArgs == 2);
 GenTree* indexOp = impStackTop().val;
if (!compSupports(InstructionSet_SSE2) || !varTypeIsArithmetic(baseType) || !indexOp->OperIsConst())
 {
// Using software fallback if
// 1. JIT/hardware don't support SSE2 instructions
// 2. baseType is not a numeric type (throw execptions)
// 3. index is not a constant
returnnullptr;
 }

switch (baseType)
 {
// Using software fallback if baseType is not supported by hardware
case TYP_BYTE:
case TYP_UBYTE:
case TYP_INT:
case TYP_UINT:
if (!compSupports(InstructionSet_SSE41))
 {
returnnullptr;
 }
break;

case TYP_LONG:
case TYP_ULONG:
if (!compSupports(InstructionSet_SSE41_X64))
 {
returnnullptr;
 }
break;

case TYP_DOUBLE:
case TYP_FLOAT:
case TYP_SHORT:
case TYP_USHORT:
// short/ushort/float/double is supported by SSE2
break;

default:
break;
 }

ssize_t imm8 = indexOp->AsIntCon()->IconValue();
ssize_t count = simdSize / genTypeSize(baseType);

if (imm8 >= count || imm8 < 0)
 {
// Using software fallback if index is out of range (throw exeception)
returnnullptr;
 }

impPopStack();
 GenTree* vectorOp = impSIMDPopStack(getSIMDTypeForSize(simdSize));
 NamedIntrinsic resIntrinsic = NI_Illegal;

if (simdSize == 32)
 {
assert(compSupports(InstructionSet_AVX));

if (imm8 >= count / 2)
 {
 imm8 -= count / 2;
 vectorOp = gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, gtNewIconNode(1), NI_AVX_ExtractVector128,
 baseType, simdSize);
 }
else
 {
 vectorOp =
gtNewSimdHWIntrinsicNode(TYP_SIMD16, vectorOp, NI_Vector256_GetLower, baseType, simdSize);
 }
 }

if (imm8 == 0 && (genTypeSize(baseType) >= 4))
 {
switch (baseType)
 {
case TYP_LONG:
 resIntrinsic = NI_SSE2_X64_ConvertToInt64;
break;

case TYP_ULONG:
 resIntrinsic = NI_SSE2_X64_ConvertToUInt64;
break;

case TYP_INT:
 resIntrinsic = NI_SSE2_ConvertToInt32;
break;

case TYP_UINT:
 resIntrinsic = NI_SSE2_ConvertToUInt32;
break;

case TYP_FLOAT:
case TYP_DOUBLE:
 resIntrinsic = NI_Vector128_ToScalar;
break;

default:
unreached();
 }

returngtNewSimdHWIntrinsicNode(retType, vectorOp, resIntrinsic, baseType, 16);
 }

 GenTree* immNode = gtNewIconNode(imm8);

switch (baseType)
 {
case TYP_LONG:
case TYP_ULONG:
 retNode = gtNewSimdHWIntrinsicNode(retType, vectorOp, immNode, NI_SSE41_X64_Extract, baseType, 16);
break;

case TYP_FLOAT:
 {
if (!compSupports(InstructionSet_SSE41))