emitxarch.h

// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

#if defined(_TARGET_XARCH_)

/************************************************************************/
/* Public inline informational methods */
/************************************************************************/

public:
inlinestaticboolisGeneralRegister(regNumber reg)
{
return (reg <= REG_INT_LAST);
}

inlinestaticboolisFloatReg(regNumber reg)
{
return (reg >= REG_FP_FIRST && reg <= REG_FP_LAST);
}

inlinestaticboolisDoubleReg(regNumber reg)
{
returnisFloatReg(reg);
}

/************************************************************************/
/* Routines that compute the size of / encode instructions */
/************************************************************************/

// code_t is a type used to accumulate bits of opcode + prefixes. On amd64, it must be 64 bits
// to support the REX prefixes. On both x86 and amd64, it must be 64 bits to support AVX, with
// its 3-byte VEX prefix.
typedefunsigned __int64 code_t;

structCnsVal
{
ssize_t cnsVal;
bool cnsReloc;
};

UNATIVE_OFFSET emitInsSize(code_t code);
UNATIVE_OFFSET emitInsSizeSV(code_t code, int var, int dsp);
UNATIVE_OFFSET emitInsSizeSV(instrDesc* id, code_t code, int var, int dsp);
UNATIVE_OFFSET emitInsSizeSV(instrDesc* id, code_t code, int var, int dsp, int val);
UNATIVE_OFFSET emitInsSizeRR(instrDesc* id, code_t code);
UNATIVE_OFFSET emitInsSizeRR(instrDesc* id, code_t code, int val);
UNATIVE_OFFSET emitInsSizeRR(instruction ins, regNumber reg1, regNumber reg2, emitAttr attr);
UNATIVE_OFFSET emitInsSizeAM(instrDesc* id, code_t code);
UNATIVE_OFFSET emitInsSizeAM(instrDesc* id, code_t code, int val);
UNATIVE_OFFSET emitInsSizeCV(instrDesc* id, code_t code);
UNATIVE_OFFSET emitInsSizeCV(instrDesc* id, code_t code, int val);

BYTE* emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc = nullptr);
BYTE* emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc = nullptr);
BYTE* emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc = nullptr);

BYTE* emitOutputR(BYTE* dst, instrDesc* id);
BYTE* emitOutputRI(BYTE* dst, instrDesc* id);
BYTE* emitOutputRR(BYTE* dst, instrDesc* id);
BYTE* emitOutputIV(BYTE* dst, instrDesc* id);

BYTE* emitOutputRRR(BYTE* dst, instrDesc* id);

BYTE* emitOutputLJ(BYTE* dst, instrDesc* id);

unsignedemitOutputRexOrVexPrefixIfNeeded(instruction ins, BYTE* dst, code_t& code);
unsignedemitGetRexPrefixSize(instruction ins);
unsignedemitGetVexPrefixSize(instruction ins, emitAttr attr);
unsignedemitGetPrefixSize(code_t code);
unsignedemitGetAdjustedSize(instruction ins, emitAttr attr, code_t code);

unsignedinsEncodeReg012(instruction ins, regNumber reg, emitAttr size, code_t* code);
unsignedinsEncodeReg345(instruction ins, regNumber reg, emitAttr size, code_t* code);
code_tinsEncodeReg3456(instruction ins, regNumber reg, emitAttr size, code_t code);
unsignedinsEncodeRegSIB(instruction ins, regNumber reg, code_t* code);

code_tinsEncodeMRreg(instruction ins, code_t code);
code_tinsEncodeRMreg(instruction ins, code_t code);
code_tinsEncodeMRreg(instruction ins, regNumber reg, emitAttr size, code_t code);
code_tinsEncodeRRIb(instruction ins, regNumber reg, emitAttr size);
code_tinsEncodeOpreg(instruction ins, regNumber reg, emitAttr size);

unsignedinsSSval(unsigned scale);

boolIsAVXInstruction(instruction ins);
code_tinsEncodeMIreg(instruction ins, regNumber reg, emitAttr size, code_t code);

code_tAddRexWPrefix(instruction ins, code_t code);
code_tAddRexRPrefix(instruction ins, code_t code);
code_tAddRexXPrefix(instruction ins, code_t code);
code_tAddRexBPrefix(instruction ins, code_t code);
code_tAddRexPrefix(instruction ins, code_t code);

boolEncodedBySSE38orSSE3A(instruction ins);
boolIs4ByteSSEInstruction(instruction ins);

boolAreUpper32BitsZero(regNumber reg);

boolhasRexPrefix(code_t code)
{
#ifdef _TARGET_AMD64_
constcode_t REX_PREFIX_MASK = 0xFF00000000LL;
return (code & REX_PREFIX_MASK) != 0;
#else// !_TARGET_AMD64_
returnfalse;
#endif// !_TARGET_AMD64_
}

// 3-byte VEX prefix starts with byte 0xC4
#defineVEX_PREFIX_MASK_3BYTE0xFF000000000000ULL
#defineVEX_PREFIX_CODE_3BYTE0xC4000000000000ULL

boolTakesVexPrefix(instruction ins);

// Returns true if the instruction encoding already contains VEX prefix
boolhasVexPrefix(code_t code)
{
return (code & VEX_PREFIX_MASK_3BYTE) == VEX_PREFIX_CODE_3BYTE;
}
code_tAddVexPrefix(instruction ins, code_t code, emitAttr attr);
code_tAddVexPrefixIfNeeded(instruction ins, code_t code, emitAttr size)
{
if (TakesVexPrefix(ins))
 {
 code = AddVexPrefix(ins, code, size);
 }
return code;
}
code_tAddVexPrefixIfNeededAndNotPresent(instruction ins, code_t code, emitAttr size)
{
if (TakesVexPrefix(ins) && !hasVexPrefix(code))
 {
 code = AddVexPrefix(ins, code, size);
 }
return code;
}

bool useVEXEncodings;
boolUseVEXEncoding()
{
return useVEXEncodings;
}
voidSetUseVEXEncoding(bool value)
{
 useVEXEncodings = value;
}

bool containsAVXInstruction = false;
boolContainsAVX()
{
return containsAVXInstruction;
}
voidSetContainsAVX(bool value)
{
 containsAVXInstruction = value;
}

bool contains256bitAVXInstruction = false;
boolContains256bitAVX()
{
return contains256bitAVXInstruction;
}
voidSetContains256bitAVX(bool value)
{
 contains256bitAVXInstruction = value;
}

boolIsDstDstSrcAVXInstruction(instruction ins);
boolIsDstSrcSrcAVXInstruction(instruction ins);
boolIsThreeOperandAVXInstruction(instruction ins)
{
return (IsDstDstSrcAVXInstruction(ins) || IsDstSrcSrcAVXInstruction(ins));
}
boolisAvxBlendv(instruction ins)
{
return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb;
}
boolisSse41Blendv(instruction ins)
{
return ins == INS_blendvps || ins == INS_blendvpd || ins == INS_pblendvb;
}
boolisPrefetch(instruction ins)
{
return (ins == INS_prefetcht0) || (ins == INS_prefetcht1) || (ins == INS_prefetcht2) || (ins == INS_prefetchnta);
}

/************************************************************************/
/* Debug-only routines to display instructions */
/************************************************************************/

#ifdef DEBUG

constchar* emitFPregName(unsigned reg, bool varName = true);

voidemitDispReloc(ssize_t value);
voidemitDispAddrMode(instrDesc* id, bool noDetail = false);
voidemitDispShift(instruction ins, int cnt = 0);

voidemitDispIns(instrDesc* id,
bool isNew,
bool doffs,
bool asmfm,
unsigned offs = 0,
 BYTE* code = nullptr,
size_t sz = 0,
 insGroup* ig = nullptr);

constchar* emitXMMregName(unsigned reg);
constchar* emitYMMregName(unsigned reg);

#endif

/************************************************************************/
/* Private members that deal with target-dependent instr. descriptors */
/************************************************************************/

private:
voidemitSetAmdDisp(instrDescAmd* id, ssize_t dsp);
instrDesc* emitNewInstrAmd(emitAttr attr, ssize_t dsp);
instrDesc* emitNewInstrAmdCns(emitAttr attr, ssize_t dsp, int cns);

instrDesc* emitNewInstrCallDir(int argCnt,
 VARSET_VALARG_TP GCvars,
 regMaskTP gcrefRegs,
 regMaskTP byrefRegs,
 emitAttr retSize MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize));

instrDesc* emitNewInstrCallInd(int argCnt,
ssize_t disp,
 VARSET_VALARG_TP GCvars,
 regMaskTP gcrefRegs,
 regMaskTP byrefRegs,
 emitAttr retSize MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize));

voidemitGetInsCns(instrDesc* id, CnsVal* cv);
ssize_temitGetInsAmdCns(instrDesc* id, CnsVal* cv);
voidemitGetInsDcmCns(instrDesc* id, CnsVal* cv);
ssize_temitGetInsAmdAny(instrDesc* id);

/************************************************************************/
/* Private helpers for instruction output */
/************************************************************************/

private:
insFormat emitInsModeFormat(instruction ins, insFormat base, insFormat FPld, insFormat FPst);

boolemitVerifyEncodable(instruction ins, emitAttr size, regNumber reg1, regNumber reg2 = REG_NA);

boolemitInsCanOnlyWriteSSE2OrAVXReg(instrDesc* id);

#if FEATURE_FIXED_OUT_ARGS
voidemitAdjustStackDepthPushPop(instruction ins)
{
}
voidemitAdjustStackDepth(instruction ins, ssize_t val)
{
}
#else// !FEATURE_FIXED_OUT_ARGS
voidemitAdjustStackDepthPushPop(instruction ins);
voidemitAdjustStackDepth(instruction ins, ssize_t val);
#endif// !FEATURE_FIXED_OUT_ARGS

/*****************************************************************************
*
* Convert between an index scale in bytes to a smaller encoding used for
* storage in instruction descriptors.
*/

inline emitter::opSize emitEncodeScale(size_t scale)
{
assert(scale == 1 || scale == 2 || scale == 4 || scale == 8);

return emitSizeEncode[scale - 1];
}

inline emitAttr emitDecodeScale(unsigned ensz)
{
assert(ensz < 4);

return emitter::emitSizeDecode[ensz];
}

/************************************************************************/
/* The public entry points to output instructions */
/************************************************************************/

public:
voidemitLoopAlign();

voidemitIns(instruction ins);

voidemitIns(instruction ins, emitAttr attr);

voidemitInsRMW(instruction inst, emitAttr attr, GenTreeStoreInd* storeInd, GenTree* src);

voidemitInsRMW(instruction inst, emitAttr attr, GenTreeStoreInd* storeInd);

voidemitIns_Nop(unsigned size);

voidemitIns_I(instruction ins, emitAttr attr, int val);

voidemitIns_R(instruction ins, emitAttr attr, regNumber reg);

voidemitIns_C(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fdlHnd, int offs);

voidemitIns_R_I(instruction ins, emitAttr attr, regNumber reg, ssize_t val);

voidemitIns_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2);

voidemitIns_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int ival);

voidemitIns_AR(instruction ins, emitAttr attr, regNumber base, int offs);

voidemitIns_AR_R_R(instruction ins, emitAttr attr, regNumber op2Reg, regNumber op3Reg, regNumber base, int offs);

voidemitIns_R_A(instruction ins, emitAttr attr, regNumber reg1, GenTreeIndir* indir);

voidemitIns_R_A_I(instruction ins, emitAttr attr, regNumber reg1, GenTreeIndir* indir, int ival);

voidemitIns_R_AR_I(instruction ins, emitAttr attr, regNumber reg1, regNumber base, int offs, int ival);

voidemitIns_R_C_I(instruction ins, emitAttr attr, regNumber reg1, CORINFO_FIELD_HANDLE fldHnd, int offs, int ival);

voidemitIns_R_S_I(instruction ins, emitAttr attr, regNumber reg1, int varx, int offs, int ival);

voidemitIns_R_R_A(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, GenTreeIndir* indir);

voidemitIns_R_R_AR(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber base, int offs);

voidemitIns_R_AR_R(instruction ins,
 emitAttr attr,
 regNumber reg1,
 regNumber reg2,
 regNumber base,
 regNumber index,
int scale,
int offs);

voidemitIns_R_R_C(
 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, CORINFO_FIELD_HANDLE fldHnd, int offs);

voidemitIns_R_R_S(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int varx, int offs);

voidemitIns_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3);

voidemitIns_R_R_A_I(
 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, GenTreeIndir* indir, int ival, insFormat fmt);
voidemitIns_R_R_AR_I(
 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber base, int offs, int ival);
voidemitIns_S_R_I(instruction ins, emitAttr attr, int varNum, int offs, regNumber reg, int ival);

voidemitIns_A_R_I(instruction ins, emitAttr attr, GenTreeIndir* indir, regNumber reg, int imm);

voidemitIns_R_R_C_I(
 instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, CORINFO_FIELD_HANDLE fldHnd, int offs, int ival);

voidemitIns_R_R_R_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, int ival);

voidemitIns_R_R_S_I(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, int varx, int offs, int ival);

voidemitIns_R_R_A_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op3Reg, GenTreeIndir* indir);

voidemitIns_R_R_AR_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op3Reg, regNumber base, int offs);

voidemitIns_R_R_C_R(instruction ins,
 emitAttr attr,
 regNumber targetReg,
 regNumber op1Reg,
 regNumber op3Reg,
 CORINFO_FIELD_HANDLE fldHnd,
int offs);

voidemitIns_R_R_S_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op3Reg, int varx, int offs);

voidemitIns_R_R_R_R(instruction ins, emitAttr attr, regNumber reg1, regNumber reg2, regNumber reg3, regNumber reg4);

voidemitIns_S(instruction ins, emitAttr attr, int varx, int offs);

voidemitIns_S_R(instruction ins, emitAttr attr, regNumber ireg, int varx, int offs);

voidemitIns_R_S(instruction ins, emitAttr attr, regNumber ireg, int varx, int offs);

voidemitIns_S_I(instruction ins, emitAttr attr, int varx, int offs, int val);

voidemitIns_R_C(instruction ins, emitAttr attr, regNumber reg, CORINFO_FIELD_HANDLE fldHnd, int offs);

voidemitIns_C_R(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fldHnd, regNumber reg, int offs);

voidemitIns_C_I(instruction ins, emitAttr attr, CORINFO_FIELD_HANDLE fdlHnd, int offs, int val);

voidemitIns_IJ(emitAttr attr, regNumber reg, unsigned base);

voidemitIns_J_S(instruction ins, emitAttr attr, BasicBlock* dst, int varx, int offs);

voidemitIns_R_L(instruction ins, emitAttr attr, BasicBlock* dst, regNumber reg);

voidemitIns_R_D(instruction ins, emitAttr attr, unsigned offs, regNumber reg);

voidemitIns_I_AR(instruction ins, emitAttr attr, int val, regNumber reg, int offs);

voidemitIns_I_AI(instruction ins, emitAttr attr, int val, ssize_t disp);

voidemitIns_R_AR(instruction ins, emitAttr attr, regNumber reg, regNumber base, int disp);

voidemitIns_R_AI(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp);

voidemitIns_AR_R(instruction ins, emitAttr attr, regNumber reg, regNumber base, int disp);

voidemitIns_AI_R(instruction ins, emitAttr attr, regNumber ireg, ssize_t disp);

voidemitIns_I_ARR(instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, int disp);

voidemitIns_R_ARR(instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, int disp);

voidemitIns_ARR_R(instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, int disp);

voidemitIns_I_ARX(instruction ins, emitAttr attr, int val, regNumber reg, regNumber rg2, unsigned mul, int disp);

voidemitIns_R_ARX(
 instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, unsigned scale, int disp);

voidemitIns_ARX_R(
 instruction ins, emitAttr attr, regNumber reg, regNumber base, regNumber index, unsigned scale, int disp);

voidemitIns_I_AX(instruction ins, emitAttr attr, int val, regNumber reg, unsigned mul, int disp);

voidemitIns_R_AX(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp);

voidemitIns_AX_R(instruction ins, emitAttr attr, regNumber ireg, regNumber reg, unsigned mul, int disp);

#ifdef FEATURE_HW_INTRINSICS
voidemitIns_SIMD_R_R_I(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, int ival);

voidemitIns_SIMD_R_R_A(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, GenTreeIndir* indir);
voidemitIns_SIMD_R_R_AR(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber base, int offset);
voidemitIns_SIMD_R_R_C(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, CORINFO_FIELD_HANDLE fldHnd, int offs);
voidemitIns_SIMD_R_R_R(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg);
voidemitIns_SIMD_R_R_S(instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, int varx, int offs);

voidemitIns_SIMD_R_R_A_I(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, GenTreeIndir* indir, int ival);
voidemitIns_SIMD_R_R_AR_I(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber base, int ival);
voidemitIns_SIMD_R_R_C_I(instruction ins,
 emitAttr attr,
 regNumber targetReg,
 regNumber op1Reg,
 CORINFO_FIELD_HANDLE fldHnd,
int offs,
int ival);
voidemitIns_SIMD_R_R_R_I(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, int ival);
voidemitIns_SIMD_R_R_S_I(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, int varx, int offs, int ival);

voidemitIns_SIMD_R_R_R_A(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, GenTreeIndir* indir);
voidemitIns_SIMD_R_R_R_AR(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, regNumber base);
voidemitIns_SIMD_R_R_R_C(instruction ins,
 emitAttr attr,
 regNumber targetReg,
 regNumber op1Reg,
 regNumber op2Reg,
 CORINFO_FIELD_HANDLE fldHnd,
int offs);
voidemitIns_SIMD_R_R_R_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, regNumber op3Reg);
voidemitIns_SIMD_R_R_R_S(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, int varx, int offs);

voidemitIns_SIMD_R_R_A_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, GenTreeIndir* indir);
voidemitIns_SIMD_R_R_AR_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, regNumber base);
voidemitIns_SIMD_R_R_C_R(instruction ins,
 emitAttr attr,
 regNumber targetReg,
 regNumber op1Reg,
 regNumber op2Reg,
 CORINFO_FIELD_HANDLE fldHnd,
int offs);
voidemitIns_SIMD_R_R_S_R(
 instruction ins, emitAttr attr, regNumber targetReg, regNumber op1Reg, regNumber op2Reg, int varx, int offs);
#endif// FEATURE_HW_INTRINSICS

enum EmitCallType
{
 EC_FUNC_TOKEN, // Direct call to a helper/static/nonvirtual/global method
 EC_FUNC_TOKEN_INDIR, // Indirect call to a helper/static/nonvirtual/global method
 EC_FUNC_ADDR, // Direct call to an absolute address

 EC_FUNC_VIRTUAL, // Call to a virtual method (using the vtable)
 EC_INDIR_R, // Indirect call via register
 EC_INDIR_SR, // Indirect call via stack-reference (local var)
 EC_INDIR_C, // Indirect call via static class var
 EC_INDIR_ARD, // Indirect call via an addressing mode

 EC_COUNT
};

// clang-format off
voidemitIns_Call(EmitCallType callType,
 CORINFO_METHOD_HANDLE methHnd,
INDEBUG_LDISASM_COMMA(CORINFO_SIG_INFO* sigInfo) // used to report call sites to the EE
 void* addr,
 ssize_t argSize,
 emitAttr retSize
 MULTIREG_HAS_SECOND_GC_RET_ONLY_ARG(emitAttr secondRetSize),
 VARSET_VALARG_TP ptrVars,
 regMaskTP gcrefRegs,
 regMaskTP byrefRegs,
 IL_OFFSETX ilOffset = BAD_IL_OFFSET,
 regNumber ireg = REG_NA,
 regNumber xreg = REG_NA,
 unsigned xmul = 0,
 ssize_t disp = 0,
 bool isJump = false);
// clang-format on

#ifdef _TARGET_AMD64_
// Is the last instruction emitted a call instruction?
boolemitIsLastInsCall();

// Insert a NOP at the end of the the current instruction group if the last emitted instruction was a 'call',
// because the next instruction group will be an epilog.
voidemitOutputPreEpilogNOP();
#endif// _TARGET_AMD64_

/*****************************************************************************
 *
 * Given a jump, return true if it's a conditional jump.
*/

inlineboolemitIsCondJump(instrDesc* jmp)
{
 instruction ins = jmp->idIns();

assert(jmp->idInsFmt() == IF_LABEL);

return (ins != INS_call && ins != INS_jmp);
}

/*****************************************************************************
 *
 * Given a jump, return true if it's an unconditional jump.
*/

inlineboolemitIsUncondJump(instrDesc* jmp)
{
 instruction ins = jmp->idIns();

assert(jmp->idInsFmt() == IF_LABEL);

return (ins == INS_jmp);
}

#endif // _TARGET_XARCH_