emitxarch.cpp

// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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XX emitX86.cpp XX
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*/

#include"jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif

#if defined(_TARGET_XARCH_)

/*****************************************************************************/
/*****************************************************************************/

#include"instr.h"
#include"emit.h"
#include"codegen.h"

boolIsSSEInstruction(instruction ins)
{
return (ins >= INS_FIRST_SSE_INSTRUCTION) && (ins <= INS_LAST_SSE_INSTRUCTION);
}

boolIsSSEOrAVXInstruction(instruction ins)
{
return (ins >= INS_FIRST_SSE_INSTRUCTION) && (ins <= INS_LAST_AVX_INSTRUCTION);
}

boolIsAVXOnlyInstruction(instruction ins)
{
return (ins >= INS_FIRST_AVX_INSTRUCTION) && (ins <= INS_LAST_AVX_INSTRUCTION);
}

boolIsFMAInstruction(instruction ins)
{
return (ins >= INS_FIRST_FMA_INSTRUCTION) && (ins <= INS_LAST_FMA_INSTRUCTION);
}

boolIsBMIInstruction(instruction ins)
{
return (ins >= INS_FIRST_BMI_INSTRUCTION) && (ins <= INS_LAST_BMI_INSTRUCTION);
}

regNumber getBmiRegNumber(instruction ins)
{
switch (ins)
 {
case INS_blsi:
 {
return (regNumber)3;
 }

case INS_blsmsk:
 {
return (regNumber)2;
 }

case INS_blsr:
 {
return (regNumber)1;
 }

default:
 {
assert(IsBMIInstruction(ins));
return REG_NA;
 }
 }
}

regNumber getSseShiftRegNumber(instruction ins)
{
switch (ins)
 {
case INS_psrldq:
 {
return (regNumber)3;
 }

case INS_pslldq:
 {
return (regNumber)7;
 }

case INS_psrld:
case INS_psrlw:
case INS_psrlq:
 {
return (regNumber)2;
 }

case INS_pslld:
case INS_psllw:
case INS_psllq:
 {
return (regNumber)6;
 }

case INS_psrad:
case INS_psraw:
 {
return (regNumber)4;
 }

default:
 {
assert(!"Invalid instruction for SSE2 instruction of the form: opcode reg, immed8");
return REG_NA;
 }
 }
}

boolemitter::IsAVXInstruction(instruction ins)
{
returnUseVEXEncoding() && IsSSEOrAVXInstruction(ins);
}

// Returns true if the AVX instruction is a binary operator that requires 3 operands.
// When we emit an instruction with only two operands, we will duplicate the destination
// as a source.
// TODO-XArch-Cleanup: This is a temporary solution for now. Eventually this needs to
// be formalized by adding an additional field to instruction table to
// to indicate whether a 3-operand instruction.
boolemitter::IsDstDstSrcAVXInstruction(instruction ins)
{
return ((CodeGenInterface::instInfo[ins] & INS_Flags_IsDstDstSrcAVXInstruction) != 0) && IsAVXInstruction(ins);
}

// Returns true if the AVX instruction requires 3 operands that duplicate the source
// register in the vvvv field.
// TODO-XArch-Cleanup: This is a temporary solution for now. Eventually this needs to
// be formalized by adding an additional field to instruction table to
// to indicate whether a 3-operand instruction.
boolemitter::IsDstSrcSrcAVXInstruction(instruction ins)
{
return ((CodeGenInterface::instInfo[ins] & INS_Flags_IsDstSrcSrcAVXInstruction) != 0) && IsAVXInstruction(ins);
}

//------------------------------------------------------------------------
// AreUpper32BitsZero: check if some previously emitted
// instruction set the upper 32 bits of reg to zero.
//
// Arguments:
// reg - register of interest
//
// Return Value:
// true if previous instruction zeroed reg's upper 32 bits.
// false if it did not, or if we can't safely determine.
//
// Notes:
// Currently only looks back one instruction.
//
// movsx eax, ... might seem viable but we always encode this
// instruction with a 64 bit destination. See TakesRexWPrefix.

boolemitter::AreUpper32BitsZero(regNumber reg)
{
// Don't look back across IG boundaries (possible control flow)
if (emitCurIGinsCnt == 0)
 {
returnfalse;
 }

 instrDesc* id = emitLastIns;
 insFormat fmt = id->idInsFmt();

// This isn't meant to be a comprehensive check. Just look for what
// seems to be common.
switch (fmt)
 {
case IF_RWR_CNS:
case IF_RRW_CNS:
case IF_RRW_SHF:
case IF_RWR_RRD:
case IF_RRW_RRD:
case IF_RWR_MRD:
case IF_RWR_SRD:
case IF_RWR_ARD:

// Bail if not writing to the right register
if (id->idReg1() != reg)
 {
returnfalse;
 }

// Bail if movsx, we always have movsx sign extend to 8 bytes
if (id->idIns() == INS_movsx)
 {
returnfalse;
 }

// movzx always zeroes the upper 32 bits.
if (id->idIns() == INS_movzx)
 {
returntrue;
 }

// Else rely on operation size.
return (id->idOpSize() == EA_4BYTE);

default:
break;
 }

returnfalse;
}

#ifdef FEATURE_HW_INTRINSICS
//------------------------------------------------------------------------
// IsDstSrcImmAvxInstruction: Checks if the instruction has a "reg, reg/mem, imm" or
// "reg/mem, reg, imm" form for the legacy, VEX, and EVEX
// encodings.
//
// Arguments:
// instruction -- processor instruction to check
//
// Return Value:
// true if instruction has a "reg, reg/mem, imm" or "reg/mem, reg, imm" encoding
// form for the legacy, VEX, and EVEX encodings.
//
// That is, the instruction takes two operands, one of which is immediate, and it
// does not need to encode any data in the VEX.vvvv field.
//
staticboolIsDstSrcImmAvxInstruction(instruction ins)
{
switch (ins)
 {
case INS_aeskeygenassist:
case INS_extractps:
case INS_pextrb:
case INS_pextrw:
case INS_pextrd:
case INS_pextrq:
case INS_pshufd:
case INS_pshufhw:
case INS_pshuflw:
case INS_roundpd:
case INS_roundps:
returntrue;
default:
returnfalse;
 }
}
#endif// FEATURE_HW_INTRINSICS

// -------------------------------------------------------------------
// Is4ByteSSEInstruction: Returns true if the SSE instruction is a 4-byte opcode.
//
// Arguments:
// ins - instruction
//
// Note that this should be true for any of the instructions in instrsXArch.h
// that use the SSE38 or SSE3A macro but returns false if the VEX encoding is
// in use, since that encoding does not require an additional byte.
boolemitter::Is4ByteSSEInstruction(instruction ins)
{
return !UseVEXEncoding() && EncodedBySSE38orSSE3A(ins);
}

// Returns true if this instruction requires a VEX prefix
// All AVX instructions require a VEX prefix
boolemitter::TakesVexPrefix(instruction ins)
{
// special case vzeroupper as it requires 2-byte VEX prefix
// special case the fencing, movnti and the prefetch instructions as they never take a VEX prefix
switch (ins)
 {
case INS_lfence:
case INS_mfence:
case INS_movnti:
case INS_prefetchnta:
case INS_prefetcht0:
case INS_prefetcht1:
case INS_prefetcht2:
case INS_sfence:
case INS_vzeroupper:
returnfalse;
default:
break;
 }

returnIsAVXInstruction(ins);
}

// Add base VEX prefix without setting W, R, X, or B bits
// L bit will be set based on emitter attr.
//
// 2-byte VEX prefix = C5 <R,vvvv,L,pp>
// 3-byte VEX prefix = C4 <R,X,B,m-mmmm> <W,vvvv,L,pp>
// - R, X, B, W - bits to express corresponding REX prefixes
// - m-mmmmm (5-bit)
// 0-00001 - implied leading 0F opcode byte
// 0-00010 - implied leading 0F 38 opcode bytes
// 0-00011 - implied leading 0F 3A opcode bytes
// Rest - reserved for future use and usage of them will uresult in Undefined instruction exception
//
// - vvvv (4-bits) - register specifier in 1's complement form; must be 1111 if unused
// - L - scalar or AVX-128 bit operations (L=0), 256-bit operations (L=1)
// - pp (2-bits) - opcode extension providing equivalent functionality of a SIMD size prefix
// these prefixes are treated mandatory when used with escape opcode 0Fh for
// some SIMD instructions
// 00 - None (0F - packed float)
// 01 - 66 (66 0F - packed double)
// 10 - F3 (F3 0F - scalar float
// 11 - F2 (F2 0F - scalar double)
#defineDEFAULT_3BYTE_VEX_PREFIX0xC4E07800000000ULL
#defineDEFAULT_3BYTE_VEX_PREFIX_MASK0xFFFFFF00000000ULL
#defineLBIT_IN_3BYTE_VEX_PREFIX0x00000400000000ULL
emitter::code_temitter::AddVexPrefix(instruction ins, code_t code, emitAttr attr)
{
// The 2-byte VEX encoding is preferred when possible, but actually emitting
// it depends on a number of factors that we may not know until much later.
//
// In order to handle this "easily", we just carry the 3-byte encoding all
// the way through and "fix-up" the encoding when the VEX prefix is actually
// emitted, by simply checking that all the requirements were met.

// Only AVX instructions require VEX prefix
assert(IsAVXInstruction(ins));

// Shouldn't have already added VEX prefix
assert(!hasVexPrefix(code));

assert((code & DEFAULT_3BYTE_VEX_PREFIX_MASK) == 0);

 code |= DEFAULT_3BYTE_VEX_PREFIX;

if (attr == EA_32BYTE)
 {
// Set L bit to 1 in case of instructions that operate on 256-bits.
 code |= LBIT_IN_3BYTE_VEX_PREFIX;
 }

return code;
}

// Returns true if this instruction, for the given EA_SIZE(attr), will require a REX.W prefix
boolTakesRexWPrefix(instruction ins, emitAttr attr)
{
// Because the current implementation of AVX does not have a way to distinguish between the register
// size specification (128 vs. 256 bits) and the operand size specification (32 vs. 64 bits), where both are
// required, the instruction must be created with the register size attribute (EA_16BYTE or EA_32BYTE),
// and here we must special case these by the opcode.
switch (ins)
 {
case INS_vpermpd:
case INS_vpermq:
case INS_vpsrlvq:
case INS_vpsllvq:
case INS_pinsrq:
case INS_pextrq:
case INS_vfmadd132pd:
case INS_vfmadd213pd:
case INS_vfmadd231pd:
case INS_vfmadd132sd:
case INS_vfmadd213sd:
case INS_vfmadd231sd:
case INS_vfmaddsub132pd:
case INS_vfmaddsub213pd:
case INS_vfmaddsub231pd:
case INS_vfmsubadd132pd:
case INS_vfmsubadd213pd:
case INS_vfmsubadd231pd:
case INS_vfmsub132pd:
case INS_vfmsub213pd:
case INS_vfmsub231pd:
case INS_vfmsub132sd:
case INS_vfmsub213sd:
case INS_vfmsub231sd:
case INS_vfnmadd132pd:
case INS_vfnmadd213pd:
case INS_vfnmadd231pd:
case INS_vfnmadd132sd:
case INS_vfnmadd213sd:
case INS_vfnmadd231sd:
case INS_vfnmsub132pd:
case INS_vfnmsub213pd:
case INS_vfnmsub231pd:
case INS_vfnmsub132sd:
case INS_vfnmsub213sd:
case INS_vfnmsub231sd:
case INS_vpmaskmovq:
case INS_vpgatherdq:
case INS_vpgatherqq:
case INS_vgatherdpd:
case INS_vgatherqpd:
returntrue;
default:
break;
 }

#ifdef _TARGET_AMD64_
// movsx should always sign extend out to 8 bytes just because we don't track
// whether the dest should be 4 bytes or 8 bytes (attr indicates the size
// of the source, not the dest).
// A 4-byte movzx is equivalent to an 8 byte movzx, so it is not special
// cased here.
//
// Rex_jmp = jmp with rex prefix always requires rex.w prefix.
if (ins == INS_movsx || ins == INS_rex_jmp)
 {
returntrue;
 }

if (EA_SIZE(attr) != EA_8BYTE)
 {
returnfalse;
 }

if (IsSSEOrAVXInstruction(ins))
 {
switch (ins)
 {
case INS_andn:
case INS_bextr:
case INS_blsi:
case INS_blsmsk:
case INS_blsr:
case INS_bzhi:
case INS_cvttsd2si:
case INS_cvttss2si:
case INS_cvtsd2si:
case INS_cvtss2si:
case INS_cvtsi2sd:
case INS_cvtsi2ss:
case INS_mov_xmm2i:
case INS_mov_i2xmm:
case INS_movnti:
case INS_mulx:
case INS_pdep:
case INS_pext:
returntrue;
default:
returnfalse;
 }
 }

// TODO-XArch-Cleanup: Better way to not emit REX.W when we don't need it, than just testing all these
// opcodes...
// These are all the instructions that default to 8-byte operand without the REX.W bit
// With 1 special case: movzx because the 4 byte version still zeros-out the hi 4 bytes
// so we never need it
if ((ins != INS_push) && (ins != INS_pop) && (ins != INS_movq) && (ins != INS_movzx) && (ins != INS_push_hide) &&
 (ins != INS_pop_hide) && (ins != INS_ret) && (ins != INS_call) && !((ins >= INS_i_jmp) && (ins <= INS_l_jg)))
 {
returntrue;
 }
else
 {
returnfalse;
 }
#else//!_TARGET_AMD64 = _TARGET_X86_
returnfalse;
#endif//!_TARGET_AMD64_
}

// Returns true if using this register will require a REX.* prefix.
// Since XMM registers overlap with YMM registers, this routine
// can also be used to know whether a YMM register if the
// instruction in question is AVX.
boolIsExtendedReg(regNumber reg)
{
#ifdef _TARGET_AMD64_
return ((reg >= REG_R8) && (reg <= REG_R15)) || ((reg >= REG_XMM8) && (reg <= REG_XMM15));
#else
// X86 JIT operates in 32-bit mode and hence extended reg are not available.
returnfalse;
#endif
}

// Returns true if using this register, for the given EA_SIZE(attr), will require a REX.* prefix
boolIsExtendedReg(regNumber reg, emitAttr attr)
{
#ifdef _TARGET_AMD64_
// Not a register, so doesn't need a prefix
if (reg > REG_XMM15)
 {
returnfalse;
 }

// Opcode field only has 3 bits for the register, these high registers
// need a 4th bit, that comes from the REX prefix (eiter REX.X, REX.R, or REX.B)
if (IsExtendedReg(reg))
 {
returntrue;
 }

if (EA_SIZE(attr) != EA_1BYTE)
 {
returnfalse;
 }

// There are 12 one byte registers addressible 'below' r8b:
// al, cl, dl, bl, ah, ch, dh, bh, spl, bpl, sil, dil.
// The first 4 are always addressible, the last 8 are divided into 2 sets:
// ah, ch, dh, bh
// -- or --
// spl, bpl, sil, dil
// Both sets are encoded exactly the same, the difference is the presence
// of a REX prefix, even a REX prefix with no other bits set (0x40).
// So in order to get to the second set we need a REX prefix (but no bits).
//
// TODO-AMD64-CQ: if we ever want to start using the first set, we'll need a different way of
// encoding/tracking/encoding registers.
return (reg >= REG_RSP);
#else
// X86 JIT operates in 32-bit mode and hence extended reg are not available.
returnfalse;
#endif
}

// Since XMM registers overlap with YMM registers, this routine
// can also used to know whether a YMM register in case of AVX instructions.
boolIsXMMReg(regNumber reg)
{
#ifdef _TARGET_AMD64_
return (reg >= REG_XMM0) && (reg <= REG_XMM15);
#else// !_TARGET_AMD64_
return (reg >= REG_XMM0) && (reg <= REG_XMM7);
#endif// !_TARGET_AMD64_
}

// Returns bits to be encoded in instruction for the given register.
unsignedRegEncoding(regNumber reg)
{
static_assert((REG_XMM0 & 0x7) == 0, "bad XMMBASE");
return (unsigned)(reg & 0x7);
}

// Utility routines that abstract the logic of adding REX.W, REX.R, REX.X, REX.B and REX prefixes
// SSE2: separate 1-byte prefix gets added before opcode.
// AVX: specific bits within VEX prefix need to be set in bit-inverted form.
emitter::code_temitter::AddRexWPrefix(instruction ins, code_t code)
{
if (UseVEXEncoding() && IsAVXInstruction(ins))
 {
if (TakesVexPrefix(ins))
 {
// W-bit is available only in 3-byte VEX prefix that starts with byte C4.
assert(hasVexPrefix(code));

// W-bit is the only bit that is added in non bit-inverted form.
returnemitter::code_t(code | 0x00008000000000ULL);
 }
 }
#ifdef _TARGET_AMD64_
returnemitter::code_t(code | 0x4800000000ULL);
#else
assert(!"UNREACHED");
return code;
#endif
}

#ifdef _TARGET_AMD64_

emitter::code_temitter::AddRexRPrefix(instruction ins, code_t code)
{
if (UseVEXEncoding() && IsAVXInstruction(ins))
 {
if (TakesVexPrefix(ins))
 {
// R-bit is supported by both 2-byte and 3-byte VEX prefix
assert(hasVexPrefix(code));

// R-bit is added in bit-inverted form.
return code & 0xFF7FFFFFFFFFFFULL;
 }
 }

return code | 0x4400000000ULL;
}

emitter::code_temitter::AddRexXPrefix(instruction ins, code_t code)
{
if (UseVEXEncoding() && IsAVXInstruction(ins))
 {
if (TakesVexPrefix(ins))
 {
// X-bit is available only in 3-byte VEX prefix that starts with byte C4.
assert(hasVexPrefix(code));

// X-bit is added in bit-inverted form.
return code & 0xFFBFFFFFFFFFFFULL;
 }
 }

return code | 0x4200000000ULL;
}

emitter::code_temitter::AddRexBPrefix(instruction ins, code_t code)
{
if (UseVEXEncoding() && IsAVXInstruction(ins))
 {
if (TakesVexPrefix(ins))
 {
// B-bit is available only in 3-byte VEX prefix that starts with byte C4.
assert(hasVexPrefix(code));

// B-bit is added in bit-inverted form.
return code & 0xFFDFFFFFFFFFFFULL;
 }
 }

return code | 0x4100000000ULL;
}

// Adds REX prefix (0x40) without W, R, X or B bits set
emitter::code_temitter::AddRexPrefix(instruction ins, code_t code)
{
assert(!UseVEXEncoding() || !IsAVXInstruction(ins));
return code | 0x4000000000ULL;
}

#endif//_TARGET_AMD64_

boolisPrefix(BYTE b)
{
assert(b != 0); // Caller should check this
assert(b != 0x67); // We don't use the address size prefix
assert(b != 0x65); // The GS segment override prefix is emitted separately
assert(b != 0x64); // The FS segment override prefix is emitted separately
assert(b != 0xF0); // The lock prefix is emitted separately
assert(b != 0x2E); // We don't use the CS segment override prefix
assert(b != 0x3E); // Or the DS segment override prefix
assert(b != 0x26); // Or the ES segment override prefix
assert(b != 0x36); // Or the SS segment override prefix

// That just leaves the size prefixes used in SSE opcodes:
// Scalar Double Scalar Single Packed Double
return ((b == 0xF2) || (b == 0xF3) || (b == 0x66));
}

// Outputs VEX prefix (in case of AVX instructions) and REX.R/X/W/B otherwise.
unsignedemitter::emitOutputRexOrVexPrefixIfNeeded(instruction ins, BYTE* dst, code_t& code)
{
if (hasVexPrefix(code))
 {
// Only AVX instructions should have a VEX prefix
assert(UseVEXEncoding() && IsAVXInstruction(ins));
code_t vexPrefix = (code >> 32) & 0x00FFFFFF;
 code &= 0x00000000FFFFFFFFLL;

 WORD leadingBytes = 0;
 BYTE check = (code >> 24) & 0xFF;
if (check != 0)
 {
// 3-byte opcode: with the bytes ordered as 0x2211RM33 or
// 4-byte opcode: with the bytes ordered as 0x22114433
// check for a prefix in the 11 position
 BYTE sizePrefix = (code >> 16) & 0xFF;
if ((sizePrefix != 0) && isPrefix(sizePrefix))
 {
// 'pp' bits in byte2 of VEX prefix allows us to encode SIMD size prefixes as two bits
//
// 00 - None (0F - packed float)
// 01 - 66 (66 0F - packed double)
// 10 - F3 (F3 0F - scalar float
// 11 - F2 (F2 0F - scalar double)
switch (sizePrefix)
 {
case0x66:
if (IsBMIInstruction(ins))
 {
switch (ins)
 {
case INS_pdep:
case INS_mulx:
 {
 vexPrefix |= 0x03;
break;
 }

case INS_pext:
 {
 vexPrefix |= 0x02;
break;
 }

default:
 {
 vexPrefix |= 0x00;
break;
 }
 }
 }
else
 {
 vexPrefix |= 0x01;
 }
break;
case0xF3:
 vexPrefix |= 0x02;
break;
case0xF2:
 vexPrefix |= 0x03;
break;
default:
assert(!"unrecognized SIMD size prefix");
unreached();
 }

// Now the byte in the 22 position must be an escape byte 0F
 leadingBytes = check;
assert(leadingBytes == 0x0F);

// Get rid of both sizePrefix and escape byte
 code &= 0x0000FFFFLL;

// Check the byte in the 33 position to see if it is 3A or 38.
// In such a case escape bytes must be 0x0F3A or 0x0F38
 check = code & 0xFF;
if (check == 0x3A || check == 0x38)
 {
 leadingBytes = (leadingBytes << 8) | check;
 code &= 0x0000FF00LL;
 }
 }
 }
else
 {
// 2-byte opcode with the bytes ordered as 0x0011RM22
// the byte in position 11 must be an escape byte.
 leadingBytes = (code >> 16) & 0xFF;
assert(leadingBytes == 0x0F || leadingBytes == 0x00);
 code &= 0xFFFF;
 }

// If there is an escape byte it must be 0x0F or 0x0F3A or 0x0F38
// m-mmmmm bits in byte 1 of VEX prefix allows us to encode these
// implied leading bytes. 0x0F is supported by both the 2-byte and
// 3-byte encoding. While 0x0F3A and 0x0F38 are only supported by
// the 3-byte version.

switch (leadingBytes)
 {
case0x00:
// there is no leading byte
break;
case0x0F:
 vexPrefix |= 0x0100;
break;
case0x0F38:
 vexPrefix |= 0x0200;
break;
case0x0F3A:
 vexPrefix |= 0x0300;
break;
default:
assert(!"encountered unknown leading bytes");
unreached();
 }

// At this point
// VEX.2211RM33 got transformed as VEX.0000RM33
// VEX.0011RM22 got transformed as VEX.0000RM22
//
// Now output VEX prefix leaving the 4-byte opcode

// The 2-byte VEX encoding, requires that the X and B-bits are set (these
// bits are inverted from the REX values so set means off), the W-bit is
// not set (this bit is not inverted), and that the m-mmmm bits are 0-0001
// (the 2-byte VEX encoding only supports the 0x0F leading byte). When these
// conditions are met, we can change byte-0 from 0xC4 to 0xC5 and then
// byte-1 is the logical-or of bit 7 from byte-1 and bits 0-6 from byte 2
// from the 3-byte VEX encoding.
//
// Given the above, the check can be reduced to a simple mask and comparison.
// * 0xFFFF7F80 is a mask that ignores any bits whose value we don't care about:
// * R can be set or unset (0x7F ignores bit 7)
// * vvvv can be any value (0x80 ignores bits 3-6)
// * L can be set or unset (0x80 ignores bit 2)
// * pp can be any value (0x80 ignores bits 0-1)
// * 0x00C46100 is a value that signifies the requirements listed above were met:
// * We must be a three-byte VEX opcode (0x00C4)
// * X and B must be set (0x61 validates bits 5-6)
// * m-mmmm must be 0-00001 (0x61 validates bits 0-4)
// * W must be unset (0x00 validates bit 7)
if ((vexPrefix & 0xFFFF7F80) == 0x00C46100)
 {
emitOutputByte(dst, 0xC5);
emitOutputByte(dst + 1, ((vexPrefix >> 8) & 0x80) | (vexPrefix & 0x7F));
return2;
 }

emitOutputByte(dst, ((vexPrefix >> 16) & 0xFF));
emitOutputByte(dst + 1, ((vexPrefix >> 8) & 0xFF));
emitOutputByte(dst + 2, vexPrefix & 0xFF);
return3;
 }

#ifdef _TARGET_AMD64_
if (code > 0x00FFFFFFFFLL)
 {
 BYTE prefix = (code >> 32) & 0xFF;
noway_assert(prefix >= 0x40 && prefix <= 0x4F);
 code &= 0x00000000FFFFFFFFLL;

// TODO-AMD64-Cleanup: when we remove the prefixes (just the SSE opcodes right now)
// we can remove this code as well

// The REX prefix is required to come after all other prefixes.
// Some of our 'opcodes' actually include some prefixes, if that
// is the case, shift them over and place the REX prefix after
// the other prefixes, and emit any prefix that got moved out.
 BYTE check = (code >> 24) & 0xFF;
if (check == 0)
 {
// 3-byte opcode: with the bytes ordered as 0x00113322
// check for a prefix in the 11 position
 check = (code >> 16) & 0xFF;
if (check != 0 && isPrefix(check))
 {
// Swap the rex prefix and whatever this prefix is
 code = (((DWORD)prefix << 16) | (code & 0x0000FFFFLL));
// and then emit the other prefix
returnemitOutputByte(dst, check);
 }
 }
else
 {
// 4-byte opcode with the bytes ordered as 0x22114433
// first check for a prefix in the 11 position
 BYTE check2 = (code >> 16) & 0xFF;
if (isPrefix(check2))
 {
assert(!isPrefix(check)); // We currently don't use this, so it is untested
if (isPrefix(check))
 {
// 3 prefixes were rex = rr, check = c1, check2 = c2 encoded as 0xrrc1c2XXXX
// Change to c2rrc1XXXX, and emit check2 now
 code = (((code_t)prefix << 24) | ((code_t)check << 16) | (code & 0x0000FFFFLL));
 }
else
 {
// 2 prefixes were rex = rr, check2 = c2 encoded as 0xrrXXc2XXXX, (check is part of the opcode)
// Change to c2XXrrXXXX, and emit check2 now
 code = (((code_t)check << 24) | ((code_t)prefix << 16) | (code & 0x0000FFFFLL));
 }
returnemitOutputByte(dst, check2);
 }
 }

returnemitOutputByte(dst, prefix);
 }
#endif// _TARGET_AMD64_

return0;
}

#ifdef _TARGET_AMD64_
/*****************************************************************************
 * Is the last instruction emitted a call instruction?
*/
boolemitter::emitIsLastInsCall()
{
if ((emitLastIns != nullptr) && (emitLastIns->idIns() == INS_call))
 {
returntrue;
 }

returnfalse;
}

/*****************************************************************************
 * We're about to create an epilog. If the last instruction we output was a 'call',
 * then we need to insert a NOP, to allow for proper exception-handling behavior.
*/
voidemitter::emitOutputPreEpilogNOP()
{
if (emitIsLastInsCall())
 {
emitIns(INS_nop);
 }
}

#endif//_TARGET_AMD64_

// Size of rex prefix in bytes
unsignedemitter::emitGetRexPrefixSize(instruction ins)
{
// In case of AVX instructions, REX prefixes are part of VEX prefix.
// And hence requires no additional byte to encode REX prefixes.
if (IsAVXInstruction(ins))
 {
return0;
 }

// If not AVX, then we would need 1-byte to encode REX prefix.
return1;
}

// Size of vex prefix in bytes
unsignedemitter::emitGetVexPrefixSize(instruction ins, emitAttr attr)
{
if (IsAVXInstruction(ins))
 {
return3;
 }

// If not AVX, then we don't need to encode vex prefix.
return0;
}

//------------------------------------------------------------------------
// emitGetAdjustedSize: Determines any size adjustment needed for a given instruction based on the current
// configuration.
//
// Arguments:
// ins -- The instruction being emitted
// attr -- The emit attribute
// code -- The current opcode and any known prefixes
unsignedemitter::emitGetAdjustedSize(instruction ins, emitAttr attr, code_t code)
{
unsigned adjustedSize = 0;

if (IsAVXInstruction(ins))
 {
// VEX prefix encodes some bytes of the opcode and as a result, overall size of the instruction reduces.
// Therefore, to estimate the size adding VEX prefix size and size of instruction opcode bytes will always
// overstimate.
// Instead this routine will adjust the size of VEX prefix based on the number of bytes of opcode it encodes so
// that
// instruction size estimate will be accurate.
// Basically this will decrease the vexPrefixSize, so that opcodeSize + vexPrefixAdjustedSize will be the right
// size.
//
// rightOpcodeSize + vexPrefixSize
// = (opcodeSize - ExtrabytesSize) + vexPrefixSize
// = opcodeSize + (vexPrefixSize - ExtrabytesSize)
// = opcodeSize + vexPrefixAdjustedSize

unsigned vexPrefixAdjustedSize = emitGetVexPrefixSize(ins, attr);
assert(vexPrefixAdjustedSize == 3);

// In this case, opcode will contains escape prefix at least one byte,
// vexPrefixAdjustedSize should be minus one.
 vexPrefixAdjustedSize -= 1;

// Get the fourth byte in Opcode.
// If this byte is non-zero, then we should check whether the opcode contains SIMD prefix or not.
 BYTE check = (code >> 24) & 0xFF;
if (check != 0)
 {
// 3-byte opcode: with the bytes ordered as 0x2211RM33 or
// 4-byte opcode: with the bytes ordered as 0x22114433
// Simd prefix is at the first byte.
 BYTE sizePrefix = (code >> 16) & 0xFF;
if (sizePrefix != 0 && isPrefix(sizePrefix))
 {
 vexPrefixAdjustedSize -= 1;
 }

// If the opcode size is 4 bytes, then the second escape prefix is at fourth byte in opcode.
// But in this case the opcode has not counted R\M part.
// opcodeSize + VexPrefixAdjustedSize - ExtraEscapePrefixSize + ModR\MSize
//=opcodeSize + VexPrefixAdjustedSize -1 + 1
//=opcodeSize + VexPrefixAdjustedSize
// So although we may have second byte escape prefix, we won't decrease vexPrefixAdjustedSize.
 }

 adjustedSize = vexPrefixAdjustedSize;
 }
elseif (Is4ByteSSEInstruction(ins))
 {
// The 4-Byte SSE instructions require one additional byte to hold the ModRM byte
 adjustedSize++;
 }
else
 {
if (ins == INS_crc32)
 {
// Adjust code size for CRC32 that has 4-byte opcode but does not use SSE38 or EES3A encoding.
 adjustedSize++;
 }

if ((attr == EA_2BYTE) && (ins != INS_movzx) && (ins != INS_movsx))
 {
// Most 16-bit operand instructions will need a 0x66 prefix.
 adjustedSize++;
 }
 }

return adjustedSize;
}

// Get size of rex or vex prefix emitted in code
unsignedemitter::emitGetPrefixSize(code_t code)
{
if (hasVexPrefix(code))
 {
return3;