emitarm64.cpp

// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

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XX emitArm64.cpp XX
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*/

#include"jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif

#if defined(_TARGET_ARM64_)

/*****************************************************************************/
/*****************************************************************************/

#include"instr.h"
#include"emit.h"
#include"codegen.h"

/* static */bool emitter::strictArmAsm = true;

/*****************************************************************************/

const instruction emitJumpKindInstructions[] = {
 INS_nop,

#defineJMP_SMALL(en, rev, ins) INS_##ins,
#include"emitjmps.h"
};

const emitJumpKind emitReverseJumpKinds[] = {
 EJ_NONE,

#defineJMP_SMALL(en, rev, ins) EJ_##rev,
#include"emitjmps.h"
};

/*****************************************************************************
 * Look up the instruction for a jump kind
*/

/*static*/ instruction emitter::emitJumpKindToIns(emitJumpKind jumpKind)
{
assert((unsigned)jumpKind < ArrLen(emitJumpKindInstructions));
return emitJumpKindInstructions[jumpKind];
}

/*****************************************************************************
* Look up the jump kind for an instruction. It better be a conditional
* branch instruction with a jump kind!
*/

/*static*/ emitJumpKind emitter::emitInsToJumpKind(instruction ins)
{
for (unsigned i = 0; i < ArrLen(emitJumpKindInstructions); i++)
 {
if (ins == emitJumpKindInstructions[i])
 {
 emitJumpKind ret = (emitJumpKind)i;
assert(EJ_NONE < ret && ret < EJ_COUNT);
return ret;
 }
 }
unreached();
}

/*****************************************************************************
 * Reverse the conditional jump
*/

/*static*/ emitJumpKind emitter::emitReverseJumpKind(emitJumpKind jumpKind)
{
assert(jumpKind < EJ_COUNT);
return emitReverseJumpKinds[jumpKind];
}

/*****************************************************************************
 *
 * Return the allocated size (in bytes) of the given instruction descriptor.
*/

size_temitter::emitSizeOfInsDsc(instrDesc* id)
{
if (emitIsScnsInsDsc(id))
return SMALL_IDSC_SIZE;

assert((unsigned)id->idInsFmt() < emitFmtCount);

 ID_OPS idOp = (ID_OPS)emitFmtToOps[id->idInsFmt()];
bool isCallIns = (id->idIns() == INS_bl) || (id->idIns() == INS_blr) || (id->idIns() == INS_b_tail) ||
 (id->idIns() == INS_br_tail);
bool maybeCallIns = (id->idIns() == INS_b) || (id->idIns() == INS_br);

switch (idOp)
 {
case ID_OP_NONE:
break;

case ID_OP_JMP:
returnsizeof(instrDescJmp);

case ID_OP_CALL:
assert(isCallIns || maybeCallIns);
if (id->idIsLargeCall())
 {
/* Must be a "fat" call descriptor */
returnsizeof(instrDescCGCA);
 }
else
 {
assert(!id->idIsLargeDsp());
assert(!id->idIsLargeCns());
returnsizeof(instrDesc);
 }
break;

default:
NO_WAY("unexpected instruction descriptor format");
break;
 }

if (id->idIsLargeCns())
 {
if (id->idIsLargeDsp())
returnsizeof(instrDescCnsDsp);
else
returnsizeof(instrDescCns);
 }
else
 {
if (id->idIsLargeDsp())
returnsizeof(instrDescDsp);
else
returnsizeof(instrDesc);
 }
}

#ifdef DEBUG
/*****************************************************************************
 *
 * The following called for each recorded instruction -- use for debugging.
*/
voidemitter::emitInsSanityCheck(instrDesc* id)
{
/* What instruction format have we got? */

switch (id->idInsFmt())
 {
 instruction ins;
 emitAttr elemsize;
 emitAttr datasize;
 emitAttr dstsize;
 emitAttr srcsize;
ssize_t imm;
unsigned immShift;
ssize_tindex;
ssize_t index2;

case IF_BI_0A: // BI_0A ......iiiiiiiiii iiiiiiiiiiiiiiii simm26:00
break;

case IF_BI_0B: // BI_0B ......iiiiiiiiii iiiiiiiiiiii.... simm19:00
break;

case IF_LARGEJMP:
case IF_LARGEADR:
case IF_LARGELDC:
break;

case IF_BI_0C: // BI_0C ......iiiiiiiiii iiiiiiiiiiiiiiii simm26:00
break;

case IF_BI_1A: // BI_1A ......iiiiiiiiii iiiiiiiiiiittttt Rt simm19:00
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
break;

case IF_BI_1B: // BI_1B B.......bbbbbiii iiiiiiiiiiittttt Rt imm6, simm14:00
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
break;

case IF_BR_1A: // BR_1A ................ ......nnnnn..... Rn
assert(isGeneralRegister(id->idReg1()));
break;

case IF_BR_1B: // BR_1B ................ ......nnnnn..... Rn
assert(isGeneralRegister(id->idReg3()));
break;

case IF_LS_1A: // LS_1A .X......iiiiiiii iiiiiiiiiiittttt Rt PC imm(1MB)
assert(isGeneralRegister(id->idReg1()) || isVectorRegister(id->idReg1()));
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_2A: // LS_2A .X.......X...... ......nnnnnttttt Rt Rn
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
assert(emitGetInsSC(id) == 0);
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_2B: // LS_2B .X.......Xiiiiii iiiiiinnnnnttttt Rt Rn imm(0-4095)
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
assert(isValidUimm12(emitGetInsSC(id)));
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiPPnnnnnttttt Rt Rn imm(-256..+255) no/pre/post inc
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
assert(emitGetInsSC(id) >= -0x100);
assert(emitGetInsSC(id) < 0x100);
assert(insOptsNone(id->idInsOpt()) || insOptsIndexed(id->idInsOpt()));
break;

case IF_LS_2D: // LS_2D .Q.............. xx.xssnnnnnttttt Vt Rn
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
assert(emitGetInsSC(id) == 0);
assert(!id->idIsLclVar());
break;

case IF_LS_2E: // LS_2E .Q.............. xx.Sssnnnnnttttt Vt[] Rn
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
 elemsize = optGetElemsize(id->idInsOpt());
assert(isValidVectorIndex(id->idOpSize(), elemsize, emitGetInsSC(id)));
assert(!id->idIsLclVar());
break;

case IF_LS_3A: // LS_3A .X.......X.mmmmm oooS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // SP
if (id->idIsLclVar())
 {
assert(isGeneralRegister(codeGen->rsGetRsvdReg()));
 }
else
 {
assert(isGeneralRegister(id->idReg3()));
 }
assert(insOptsLSExtend(id->idInsOpt()));
break;

case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
assert((isValidGeneralDatasize(id->idOpSize()) && isIntegerRegister(id->idReg1())) ||
 (isValidVectorLSPDatasize(id->idOpSize()) && isVectorRegister(id->idReg1())));
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()) || // ZR
isVectorRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3())); // SP
assert(emitGetInsSC(id) == 0);
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
assert((isValidGeneralDatasize(id->idOpSize()) && isIntegerRegister(id->idReg1())) ||
 (isValidVectorLSPDatasize(id->idOpSize()) && isVectorRegister(id->idReg1())));
assert(isIntegerRegister(id->idReg1()) || // ZR
isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()) || // ZR
isVectorRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3())); // SP
assert(emitGetInsSC(id) >= -0x40);
assert(emitGetInsSC(id) < 0x40);
assert(insOptsNone(id->idInsOpt()) || insOptsIndexed(id->idInsOpt()));
break;

case IF_LS_3D: // LS_3D .X.......X.mmmmm ......nnnnnttttt Wm Rt Rn
assert(isIntegerRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3()));
assert(emitGetInsSC(id) == 0);
assert(!id->idIsLclVar());
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_3E: // LS_3E .X.........mmmmm ......nnnnnttttt Rm Rt Rn ARMv8.1 LSE Atomics
assert(isIntegerRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3()));
assert(emitGetInsSC(id) == 0);
assert(!id->idIsLclVar());
assert(insOptsNone(id->idInsOpt()));
break;

case IF_LS_3F: // LS_3F .Q.........mmmmm xx.xssnnnnnttttt Vt Rn Rm
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3()));
assert(emitGetInsSC(id) == 0);
assert(!id->idIsLclVar());
break;

case IF_LS_3G: // LS_3G .Q.........mmmmm xx.Sssnnnnnttttt Vt[] Rn Rm
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2()));
assert(isIntegerRegister(id->idReg3()));
 elemsize = optGetElemsize(id->idInsOpt());
assert(isValidVectorIndex(id->idOpSize(), elemsize, emitGetInsSC(id)));
assert(!id->idIsLclVar());
break;

case IF_DI_1A: // DI_1A X.......shiiiiii iiiiiinnnnn..... Rn imm(i12,sh)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidUimm12(emitGetInsSC(id)));
assert(insOptsNone(id->idInsOpt()) || insOptsLSL12(id->idInsOpt()));
break;

case IF_DI_1B: // DI_1B X........hwiiiii iiiiiiiiiiiddddd Rd imm(i16,hw)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidImmHWVal(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DI_1C: // DI_1C X........Nrrrrrr ssssssnnnnn..... Rn imm(N,r,s)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidImmNRS(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DI_1D: // DI_1D X........Nrrrrrr ssssss.....ddddd Rd imm(N,r,s)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isValidImmNRS(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DI_1E: // DI_1E .ii.....iiiiiiii iiiiiiiiiiiddddd Rd simm21
assert(isGeneralRegister(id->idReg1()));
break;

case IF_DI_1F: // DI_1F X..........iiiii cccc..nnnnn.nzcv Rn imm5 nzcv cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidImmCondFlagsImm5(emitGetInsSC(id)));
break;

case IF_DI_2A: // DI_2A X.......shiiiiii iiiiiinnnnnddddd Rd Rn imm(i12,sh)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isIntegerRegister(id->idReg2())); // SP
assert(isValidUimm12(emitGetInsSC(id)));
assert(insOptsNone(id->idInsOpt()) || insOptsLSL12(id->idInsOpt()));
break;

case IF_DI_2B: // DI_2B X.........Xnnnnn ssssssnnnnnddddd Rd Rn imm(0-63)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DI_2C: // DI_2C X........Nrrrrrr ssssssnnnnnddddd Rd Rn imm(N,r,s)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmNRS(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DI_2D: // DI_2D X........Nrrrrrr ssssssnnnnnddddd Rd Rn imr, imms (N,r,s)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmNRS(emitGetInsSC(id), id->idOpSize()));
break;

case IF_DR_1D: // DR_1D X............... cccc.......ddddd Rd cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isValidImmCond(emitGetInsSC(id)));
break;

case IF_DR_2A: // DR_2A X..........mmmmm ......nnnnn..... Rn Rm
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;

case IF_DR_2B: // DR_2B X.......sh.mmmmm ssssssnnnnn..... Rn Rm {LSL,LSR,ASR,ROR} imm(0-63)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // ZR
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
if (!insOptsNone(id->idInsOpt()))
 {
if (id->idIns() == INS_tst) // tst allows ROR, cmp/cmn don't
 {
assert(insOptsAnyShift(id->idInsOpt()));
 }
else
 {
assert(insOptsAluShift(id->idInsOpt()));
 }
 }
assert(insOptsNone(id->idInsOpt()) || (emitGetInsSC(id) > 0));
break;

case IF_DR_2C: // DR_2C X..........mmmmm ooosssnnnnn..... Rn Rm ext(Rm) LSL imm(0-4)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isGeneralRegister(id->idReg2()));
assert(insOptsNone(id->idInsOpt()) || insOptsLSL(id->idInsOpt()) || insOptsAnyExtend(id->idInsOpt()));
assert(emitGetInsSC(id) >= 0);
assert(emitGetInsSC(id) <= 4);
if (insOptsLSL(id->idInsOpt()))
 {
assert(emitGetInsSC(id) > 0);
 }
break;

case IF_DR_2D: // DR_2D X..........nnnnn cccc..nnnnnmmmmm Rd Rn cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmCond(emitGetInsSC(id)));
break;

case IF_DR_2E: // DR_2E X..........mmmmm ...........ddddd Rd Rm
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isIntegerRegister(id->idReg2())); // ZR
break;

case IF_DR_2F: // DR_2F X.......sh.mmmmm ssssss.....ddddd Rd Rm {LSL,LSR,ASR} imm(0-63)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
assert(insOptsNone(id->idInsOpt()) || insOptsAluShift(id->idInsOpt()));
assert(insOptsNone(id->idInsOpt()) || (emitGetInsSC(id) > 0));
break;

case IF_DR_2G: // DR_2G X............... ......nnnnnddddd Rd Rm
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isIntegerRegister(id->idReg2())); // SP
break;

case IF_DR_2H: // DR_2H X........X...... ......nnnnnddddd Rd Rn
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;

case IF_DR_2I: // DR_2I X..........mmmmm cccc..nnnnn.nzcv Rn Rm nzcv cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isValidImmCondFlags(emitGetInsSC(id)));
break;

case IF_DR_2J: // DR_2J ................ ......nnnnnddddd Sd Sn (sha1h)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DR_3A: // DR_3A X..........mmmmm ......nnnnnmmmmm Rd Rn Rm
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isIntegerRegister(id->idReg2())); // SP
if (id->idIsLclVar())
 {
assert(isGeneralRegister(codeGen->rsGetRsvdReg()));
 }
else
 {
assert(isGeneralRegister(id->idReg3()));
 }
assert(insOptsNone(id->idInsOpt()));
break;

case IF_DR_3B: // DR_3B X.......sh.mmmmm ssssssnnnnnddddd Rd Rn Rm {LSL,LSR,ASR,ROR} imm(0-63)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
assert(insOptsNone(id->idInsOpt()) || insOptsAnyShift(id->idInsOpt()));
assert(insOptsNone(id->idInsOpt()) || (emitGetInsSC(id) > 0));
break;

case IF_DR_3C: // DR_3C X..........mmmmm ooosssnnnnnddddd Rd Rn Rm ext(Rm) LSL imm(0-4)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isIntegerRegister(id->idReg1())); // SP
assert(isIntegerRegister(id->idReg2())); // SP
assert(isGeneralRegister(id->idReg3()));
assert(insOptsNone(id->idInsOpt()) || insOptsLSL(id->idInsOpt()) || insOptsAnyExtend(id->idInsOpt()));
assert(emitGetInsSC(id) >= 0);
assert(emitGetInsSC(id) <= 4);
if (insOptsLSL(id->idInsOpt()))
 {
assert((emitGetInsSC(id) > 0) ||
 (id->idReg2() == REG_ZR)); // REG_ZR encodes SP and we allow a shift of zero
 }
break;

case IF_DR_3D: // DR_3D X..........mmmmm cccc..nnnnnmmmmm Rd Rn Rm cond
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isValidImmCond(emitGetInsSC(id)));
break;

case IF_DR_3E: // DR_3E X........X.mmmmm ssssssnnnnnddddd Rd Rn Rm imm(0-63)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isValidImmShift(emitGetInsSC(id), id->idOpSize()));
assert(insOptsNone(id->idInsOpt()));
break;

case IF_DR_4A: // DR_4A X..........mmmmm .aaaaannnnnddddd Rd Rn Rm Ra
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isGeneralRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
assert(isGeneralRegister(id->idReg3()));
assert(isGeneralRegister(id->idReg4()));
break;

case IF_DV_1A: // DV_1A .........X.iiiii iii........ddddd Vd imm8 (fmov - immediate scalar)
assert(insOptsNone(id->idInsOpt()));
 elemsize = id->idOpSize();
assert(isValidVectorElemsizeFloat(elemsize));
assert(isVectorRegister(id->idReg1()));
assert(isValidUimm8(emitGetInsSC(id)));
break;

case IF_DV_1B: // DV_1B .QX..........iii cmod..iiiiiddddd Vd imm8 (immediate vector)
 ins = id->idIns();
 imm = emitGetInsSC(id) & 0x0ff;
 immShift = (emitGetInsSC(id) & 0x700) >> 8;
assert(immShift >= 0);
 datasize = id->idOpSize();
assert(isValidVectorDatasize(datasize));
assert(isValidArrangement(datasize, id->idInsOpt()));
 elemsize = optGetElemsize(id->idInsOpt());
if (ins == INS_fmov)
 {
assert(isValidVectorElemsizeFloat(elemsize));
assert(id->idInsOpt() != INS_OPTS_1D); // Reserved encoding
assert(immShift == 0);
 }
else
 {
assert(isValidVectorElemsize(elemsize));
assert((immShift != 4) && (immShift != 7)); // always invalid values
if (ins != INS_movi) // INS_mvni, INS_orr, INS_bic
 {
assert((elemsize != EA_1BYTE) && (elemsize != EA_8BYTE)); // only H or S
if (elemsize == EA_2BYTE)
 {
assert(immShift < 2);
 }
else// (elemsize == EA_4BYTE)
 {
if (ins != INS_mvni)
 {
assert(immShift < 4);
 }
 }
 }
 }
assert(isVectorRegister(id->idReg1()));
assert(isValidUimm8(imm));
break;

case IF_DV_1C: // DV_1C .........X...... ......nnnnn..... Vn #0.0 (fcmp - with zero)
assert(insOptsNone(id->idInsOpt()));
 elemsize = id->idOpSize();
assert(isValidVectorElemsizeFloat(elemsize));
assert(isVectorRegister(id->idReg1()));
break;

case IF_DV_2A: // DV_2A .Q.......X...... ......nnnnnddddd Vd Vn (fabs, fcvt - vector)
case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
case IF_DV_2P: // DV_2P ................ ......nnnnnddddd Vd Vn (aes*, sha1su1)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2N: // DV_2N .........iiiiiii ......nnnnnddddd Vd Vn imm (shift - scalar)
assert(id->idOpSize() == EA_8BYTE);
assert(insOptsNone(id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isValidImmShift(emitGetInsSC(id), EA_8BYTE));
break;

case IF_DV_2O: // DV_2O .Q.......iiiiiii ......nnnnnddddd Vd Vn imm (shift - vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
 elemsize = optGetElemsize(id->idInsOpt());
assert(isValidImmShift(emitGetInsSC(id), elemsize));
break;

case IF_DV_2B: // DV_2B .Q.........iiiii ......nnnnnddddd Rd Vn[] (umov/smov - to general)
 elemsize = id->idOpSize();
index = emitGetInsSC(id);
assert(insOptsNone(id->idInsOpt()));
assert(isValidVectorIndex(EA_16BYTE, elemsize, index));
assert(isValidVectorElemsize(elemsize));
assert(isGeneralRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2C: // DV_2C .Q.........iiiii ......nnnnnddddd Vd Rn (dup/ins - vector from general)
if (id->idIns() == INS_dup)
 {
 datasize = id->idOpSize();
assert(isValidVectorDatasize(datasize));
assert(isValidArrangement(datasize, id->idInsOpt()));
 elemsize = optGetElemsize(id->idInsOpt());
 }
else// INS_ins
 {
 datasize = EA_16BYTE;
 elemsize = id->idOpSize();
assert(isValidVectorElemsize(elemsize));
 }
assert(isVectorRegister(id->idReg1()));
assert(isGeneralRegisterOrZR(id->idReg2()));
break;

case IF_DV_2D: // DV_2D .Q.........iiiii ......nnnnnddddd Vd Vn[] (dup - vector)
 datasize = id->idOpSize();
assert(isValidVectorDatasize(datasize));
assert(isValidArrangement(datasize, id->idInsOpt()));
 elemsize = optGetElemsize(id->idInsOpt());
index = emitGetInsSC(id);
assert(isValidVectorIndex(datasize, elemsize, index));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2E: // DV_2E ...........iiiii ......nnnnnddddd Vd Vn[] (dup - scalar)
 elemsize = id->idOpSize();
index = emitGetInsSC(id);
assert(isValidVectorIndex(EA_16BYTE, elemsize, index));
assert(isValidVectorElemsize(elemsize));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2F: // DV_2F ...........iiiii .jjjj.nnnnnddddd Vd[] Vn[] (ins - element)
 imm = emitGetInsSC(id);
index = (imm >> 4) & 0xf;
 index2 = imm & 0xf;
 elemsize = id->idOpSize();
assert(isValidVectorElemsize(elemsize));
assert(isValidVectorIndex(EA_16BYTE, elemsize, index));
assert(isValidVectorIndex(EA_16BYTE, elemsize, index2));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2L: // DV_2L ........XX...... ......nnnnnddddd Vd Vn (abs, neg - scalar)
assert(id->idOpSize() == EA_8BYTE); // only type D is supported
 __fallthrough;

case IF_DV_2G: // DV_2G .........X...... ......nnnnnddddd Vd Vn (fmov, fcvtXX - register)
case IF_DV_2K: // DV_2K .........X.mmmmm ......nnnnn..... Vn Vm (fcmp)
assert(insOptsNone(id->idInsOpt()));
assert(isValidVectorElemsizeFloat(id->idOpSize()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2H: // DV_2H X........X...... ......nnnnnddddd Rd Vn (fmov/fcvtXX - to general)
assert(insOptsConvertFloatToInt(id->idInsOpt()));
 dstsize = optGetDstsize(id->idInsOpt());
 srcsize = optGetSrcsize(id->idInsOpt());
assert(isValidGeneralDatasize(dstsize));
assert(isValidVectorElemsizeFloat(srcsize));
assert(dstsize == id->idOpSize());
assert(isGeneralRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_2I: // DV_2I X........X...... ......nnnnnddddd Vd Rn (fmov/Xcvtf - from general)
assert(insOptsConvertIntToFloat(id->idInsOpt()));
 dstsize = optGetDstsize(id->idInsOpt());
 srcsize = optGetSrcsize(id->idInsOpt());
assert(isValidGeneralDatasize(srcsize));
assert(isValidVectorElemsizeFloat(dstsize));
assert(dstsize == id->idOpSize());
assert(isVectorRegister(id->idReg1()));
assert(isGeneralRegister(id->idReg2()));
break;

case IF_DV_2J: // DV_2J ........SS.....D D.....nnnnnddddd Vd Vn (fcvt)
assert(insOptsConvertFloatToFloat(id->idInsOpt()));
 dstsize = optGetDstsize(id->idInsOpt());
 srcsize = optGetSrcsize(id->idInsOpt());
assert(isValidVectorFcvtsize(srcsize));
assert(isValidVectorFcvtsize(dstsize));
assert(dstsize == id->idOpSize());
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
break;

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
 elemsize = optGetElemsize(id->idInsOpt());
 ins = id->idIns();
if (ins == INS_mul)
 {
assert(elemsize != EA_8BYTE); // can't use 2D or 1D
 }
elseif (ins == INS_pmul)
 {
assert(elemsize == EA_1BYTE); // only supports 8B or 16B
 }
break;

case IF_DV_3AI: // DV_3AI .Q......XXLMmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector by elem)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
 elemsize = optGetElemsize(id->idInsOpt());
assert(isValidVectorIndex(EA_16BYTE, elemsize, emitGetInsSC(id)));
// Only has encodings for H or S elemsize
assert((elemsize == EA_2BYTE) || (elemsize == EA_4BYTE));
break;

case IF_DV_3B: // DV_3B .Q.......X.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
break;

case IF_DV_3BI: // DV_3BI .Q.......XLmmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector by elem)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
 elemsize = optGetElemsize(id->idInsOpt());
assert(isValidVectorIndex(id->idOpSize(), elemsize, emitGetInsSC(id)));
break;

case IF_DV_3C: // DV_3C .Q.........mmmmm ......nnnnnddddd Vd Vn Vm (vector)
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
break;

case IF_DV_3D: // DV_3D .........X.mmmmm ......nnnnnddddd Vd Vn Vm (scalar)
assert(isValidScalarDatasize(id->idOpSize()));
assert(insOptsNone(id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
break;

case IF_DV_3DI: // DV_3DI .........XLmmmmm ....H.nnnnnddddd Vd Vn Vm[] (scalar by elem)
assert(isValidScalarDatasize(id->idOpSize()));
assert(insOptsNone(id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
 elemsize = id->idOpSize();
assert(isValidVectorIndex(EA_16BYTE, elemsize, emitGetInsSC(id)));
break;

case IF_DV_3E: // DV_3E ...........mmmmm ......nnnnnddddd Vd Vn Vm (scalar)
assert(insOptsNone(id->idInsOpt()));
assert(id->idOpSize() == EA_8BYTE);
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
break;

case IF_DV_3F: // DV_3F ...........mmmmm ......nnnnnddddd Vd Vn Vm
assert(isValidVectorDatasize(id->idOpSize()));
assert(isValidArrangement(id->idOpSize(), id->idInsOpt()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
break;

case IF_DV_4A: // DR_4A .........X.mmmmm .aaaaannnnnddddd Rd Rn Rm Ra (scalar)
assert(isValidGeneralDatasize(id->idOpSize()));
assert(isVectorRegister(id->idReg1()));
assert(isVectorRegister(id->idReg2()));
assert(isVectorRegister(id->idReg3()));
assert(isVectorRegister(id->idReg4()));
break;

case IF_SN_0A: // SN_0A ................ ................
case IF_SI_0A: // SI_0A ...........iiiii iiiiiiiiiii..... imm16
case IF_SI_0B: // SI_0B ................ ....bbbb........ imm4 - barrier
break;

default:
printf("unexpected format %s\n", emitIfName(id->idInsFmt()));
assert(!"Unexpected format");
break;
 }
}
#endif// DEBUG

boolemitter::emitInsMayWriteToGCReg(instrDesc* id)
{
 instruction ins = id->idIns();
 insFormat fmt = id->idInsFmt();

switch (fmt)
 {

// These are the formats with "destination" registers:

case IF_DI_1B: // DI_1B X........hwiiiii iiiiiiiiiiiddddd Rd imm(i16,hw)
case IF_DI_1D: // DI_1D X........Nrrrrrr ssssss.....ddddd Rd imm(N,r,s)
case IF_DI_1E: // DI_1E .ii.....iiiiiiii iiiiiiiiiiiddddd Rd simm21

case IF_DI_2A: // DI_2A X.......shiiiiii iiiiiinnnnnddddd Rd Rn imm(i12,sh)
case IF_DI_2B: // DI_2B X.........Xnnnnn ssssssnnnnnddddd Rd Rn imm(0-63)
case IF_DI_2C: // DI_2C X........Nrrrrrr ssssssnnnnnddddd Rd Rn imm(N,r,s)
case IF_DI_2D: // DI_2D X........Nrrrrrr ssssssnnnnnddddd Rd Rn imr, imms (N,r,s)

case IF_DR_1D: // DR_1D X............... cccc.......ddddd Rd cond

case IF_DR_2D: // DR_2D X..........nnnnn cccc..nnnnnddddd Rd Rn cond
case IF_DR_2E: // DR_2E X..........mmmmm ...........ddddd Rd Rm
case IF_DR_2F: // DR_2F X.......sh.mmmmm ssssss.....ddddd Rd Rm {LSL,LSR,ASR} imm(0-63)
case IF_DR_2G: // DR_2G X............... ......nnnnnddddd Rd Rn
case IF_DR_2H: // DR_2H X........X...... ......nnnnnddddd Rd Rn

case IF_DR_3A: // DR_3A X..........mmmmm ......nnnnnddddd Rd Rn Rm
case IF_DR_3B: // DR_3B X.......sh.mmmmm ssssssnnnnnddddd Rd Rn Rm {LSL,LSR,ASR} imm(0-63)
case IF_DR_3C: // DR_3C X..........mmmmm xxxsssnnnnnddddd Rd Rn Rm ext(Rm) LSL imm(0-4)
case IF_DR_3D: // DR_3D X..........mmmmm cccc..nnnnnddddd Rd Rn Rm cond
case IF_DR_3E: // DR_3E X........X.mmmmm ssssssnnnnnddddd Rd Rn Rm imm(0-63)
case IF_DV_3F: // DV_3F ...........mmmmm ......nnnnnddddd Vd Vn Vm (vector) - Vd both source and dest

case IF_DR_4A: // DR_4A X..........mmmmm .aaaaannnnnddddd Rd Rn Rm Ra

case IF_DV_2B: // DV_2B .Q.........iiiii ......nnnnnddddd Rd Vn[] (umov - to general)
case IF_DV_2H: // DV_2H X........X...... ......nnnnnddddd Rd Vn (fmov - to general)

returntrue;

case IF_DV_2C: // DV_2C .Q.........iiiii ......nnnnnddddd Vd Rn (dup/ins - vector from general)
case IF_DV_2D: // DV_2D .Q.........iiiii ......nnnnnddddd Vd Vn[] (dup - vector)
case IF_DV_2E: // DV_2E ...........iiiii ......nnnnnddddd Vd Vn[] (dup - scalar)
case IF_DV_2F: // DV_2F ...........iiiii .jjjj.nnnnnddddd Vd[] Vn[] (ins - element)
case IF_DV_2G: // DV_2G .........X...... ......nnnnnddddd Vd Vn (fmov, fcvtXX - register)
case IF_DV_2I: // DV_2I X........X...... ......nnnnnddddd Vd Rn (fmov - from general)
case IF_DV_2J: // DV_2J ........SS.....D D.....nnnnnddddd Vd Vn (fcvt)
case IF_DV_2K: // DV_2K .........X.mmmmm ......nnnnn..... Vn Vm (fcmp)
case IF_DV_2L: // DV_2L ........XX...... ......nnnnnddddd Vd Vn (abs, neg - scalar)
case IF_DV_2M: // DV_2M .Q......XX...... ......nnnnnddddd Vd Vn (abs, neg - vector)
case IF_DV_2P: // DV_2P ................ ......nnnnnddddd Vd Vn (aes*, sha1su1) - Vd both source and
// destination

case IF_DV_3A: // DV_3A .Q......XX.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
case IF_DV_3AI: // DV_3AI .Q......XXLMmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector)
case IF_DV_3B: // DV_3B .Q.......X.mmmmm ......nnnnnddddd Vd Vn Vm (vector)
case IF_DV_3BI: // DV_3BI .Q.......XLmmmmm ....H.nnnnnddddd Vd Vn Vm[] (vector by elem)
case IF_DV_3C: // DV_3C .Q.........mmmmm ......nnnnnddddd Vd Vn Vm (vector)
case IF_DV_3D: // DV_3D .........X.mmmmm ......nnnnnddddd Vd Vn Vm (scalar)
case IF_DV_3DI: // DV_3DI .........XLmmmmm ....H.nnnnnddddd Vd Vn Vm[] (scalar by elem)
case IF_DV_3E: // DV_3E ...........mmmmm ......nnnnnddddd Vd Vn Vm (scalar)
case IF_DV_4A: // DV_4A .........X.mmmmm .aaaaannnnnddddd Vd Va Vn Vm (scalar)
// Tracked GC pointers cannot be placed into the SIMD registers.
returnfalse;

// These are the load/store formats with "target" registers:

case IF_LS_1A: // LS_1A XX...V..iiiiiiii iiiiiiiiiiittttt Rt PC imm(1MB)
case IF_LS_2A: // LS_2A .X.......X...... ......nnnnnttttt Rt Rn
case IF_LS_2B: // LS_2B .X.......Xiiiiii iiiiiinnnnnttttt Rt Rn imm(0-4095)
case IF_LS_2C: // LS_2C .X.......X.iiiii iiiiP.nnnnnttttt Rt Rn imm(-256..+255) pre/post inc
case IF_LS_2D: // LS_2D .Q.............. xx.xssnnnnnttttt Vt Rn
case IF_LS_2E: // LS_2E .Q.............. xx.Sssnnnnnttttt Vt[] Rn
case IF_LS_3A: // LS_3A .X.......X.mmmmm xxxS..nnnnnttttt Rt Rn Rm ext(Rm) LSL {}
case IF_LS_3B: // LS_3B X............... .aaaaannnnnttttt Rt Ra Rn
case IF_LS_3C: // LS_3C X.........iiiiii iaaaaannnnnttttt Rt Ra Rn imm(im7,sh)
case IF_LS_3D: // LS_3D .X.......X.mmmmm ......nnnnnttttt Wm Rt Rn
case IF_LS_3F: // LS_3F .Q.........mmmmm xx.xssnnnnnttttt Vt Rn Rm
case IF_LS_3G: // LS_3G .Q.........mmmmm xx.Sssnnnnnttttt Vt[] Rn Rm

// For the Store instructions the "target" register is actually a "source" value

if (emitInsIsStore(ins))
 {
returnfalse;
 }
else
 {
assert(emitInsIsLoad(ins));
returntrue;
 }

case IF_LS_3E: // LS_3E .X.........mmmmm ......nnnnnttttt Rm Rt Rn ARMv8.1 LSE Atomics
// ARMv8.1 Atomics
assert(emitInsIsStore(ins));
assert(emitInsIsLoad(ins));
returntrue;

default:
returnfalse;
 }
}

boolemitter::emitInsWritesToLclVarStackLoc(instrDesc* id)
{
if (!id->idIsLclVar())
returnfalse;

 instruction ins = id->idIns();

// This list is related to the list of instructions used to store local vars in emitIns_S_R().
// We don't accept writing to float local vars.

switch (ins)
 {
case INS_strb:
case INS_strh:
case INS_str:
case INS_stur:
case INS_sturb:
case INS_sturh:
returntrue;
default:
returnfalse;
 }
}

boolemitter::emitInsWritesToLclVarStackLocPair(instrDesc* id)
{
if (!id->idIsLclVar())
returnfalse;

 instruction ins = id->idIns();

// This list is related to the list of instructions used to store local vars in emitIns_S_S_R_R().
// We don't accept writing to float local vars.

switch (ins)
 {
case INS_stnp:
case INS_stp:
returntrue;
default:
returnfalse;
 }
}

boolemitter::emitInsMayWriteMultipleRegs(instrDesc* id)
{
 instruction ins = id->idIns();

switch (ins)
 {
case INS_ldp:
case INS_ldpsw:
case INS_ldnp: