codegenarm64.cpp

// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.
// See the LICENSE file in the project root for more information.

/*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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XX XX
XX Arm64 Code Generator XX
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*/
#include"jitpch.h"
#ifdef _MSC_VER
#pragma hdrstop
#endif

#ifdef _TARGET_ARM64_
#include"emit.h"
#include"codegen.h"
#include"lower.h"
#include"gcinfo.h"
#include"gcinfoencoder.h"

/*
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XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XX XX
XX Prolog / Epilog XX
XX XX
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*/

//------------------------------------------------------------------------
// genInstrWithConstant: we will typically generate one instruction
//
// ins reg1, reg2, imm
//
// However the imm might not fit as a directly encodable immediate,
// when it doesn't fit we generate extra instruction(s) that sets up
// the 'regTmp' with the proper immediate value.
//
// mov regTmp, imm
// ins reg1, reg2, regTmp
//
// Arguments:
// ins - instruction
// attr - operation size and GC attribute
// reg1, reg2 - first and second register operands
// imm - immediate value (third operand when it fits)
// tmpReg - temp register to use when the 'imm' doesn't fit. Can be REG_NA
// if caller knows for certain the constant will fit.
// inUnwindRegion - true if we are in a prolog/epilog region with unwind codes.
// Default: false.
//
// Return Value:
// returns true if the immediate was too large and tmpReg was used and modified.
//
boolCodeGen::genInstrWithConstant(instruction ins,
 emitAttr attr,
 regNumber reg1,
 regNumber reg2,
ssize_t imm,
 regNumber tmpReg,
bool inUnwindRegion /* = false */)
{
bool immFitsInIns = false;
 emitAttr size = EA_SIZE(attr);

// reg1 is usually a dest register
// reg2 is always source register
assert(tmpReg != reg2); // regTmp can not match any source register

switch (ins)
 {
case INS_add:
case INS_sub:
if (imm < 0)
 {
 imm = -imm;
 ins = (ins == INS_add) ? INS_sub : INS_add;
 }
 immFitsInIns = emitter::emitIns_valid_imm_for_add(imm, size);
break;

case INS_strb:
case INS_strh:
case INS_str:
// reg1 is a source register for store instructions
assert(tmpReg != reg1); // regTmp can not match any source register
 immFitsInIns = emitter::emitIns_valid_imm_for_ldst_offset(imm, size);
break;

case INS_ldrsb:
case INS_ldrsh:
case INS_ldrsw:
case INS_ldrb:
case INS_ldrh:
case INS_ldr:
 immFitsInIns = emitter::emitIns_valid_imm_for_ldst_offset(imm, size);
break;

default:
assert(!"Unexpected instruction in genInstrWithConstant");
break;
 }

if (immFitsInIns)
 {
// generate a single instruction that encodes the immediate directly
GetEmitter()->emitIns_R_R_I(ins, attr, reg1, reg2, imm);
 }
else
 {
// caller can specify REG_NA for tmpReg, when it "knows" that the immediate will always fit
assert(tmpReg != REG_NA);

// generate two or more instructions

// first we load the immediate into tmpReg
instGen_Set_Reg_To_Imm(size, tmpReg, imm);
 regSet.verifyRegUsed(tmpReg);

// when we are in an unwind code region
// we record the extra instructions using unwindPadding()
if (inUnwindRegion)
 {
 compiler->unwindPadding();
 }

// generate the instruction using a three register encoding with the immediate in tmpReg
GetEmitter()->emitIns_R_R_R(ins, attr, reg1, reg2, tmpReg);
 }
return immFitsInIns;
}

//------------------------------------------------------------------------
// genStackPointerAdjustment: add a specified constant value to the stack pointer in either the prolog
// or the epilog. The unwind codes for the generated instructions are produced. An available temporary
// register is required to be specified, in case the constant is too large to encode in an "add"
// instruction (or "sub" instruction if we choose to use one), such that we need to load the constant
// into a register first, before using it.
//
// Arguments:
// spDelta - the value to add to SP (can be negative)
// tmpReg - an available temporary register
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
// reportUnwindData - If true, report the change in unwind data. Otherwise, do not report it.
//
// Return Value:
// None.

voidCodeGen::genStackPointerAdjustment(ssize_t spDelta, regNumber tmpReg, bool* pTmpRegIsZero, bool reportUnwindData)
{
// Even though INS_add is specified here, the encoder will choose either
// an INS_add or an INS_sub and encode the immediate as a positive value
//
if (genInstrWithConstant(INS_add, EA_PTRSIZE, REG_SPBASE, REG_SPBASE, spDelta, tmpReg, true))
 {
if (pTmpRegIsZero != nullptr)
 {
 *pTmpRegIsZero = false;
 }
 }

if (reportUnwindData)
 {
// spDelta is negative in the prolog, positive in the epilog, but we always tell the unwind codes the positive
// value.
ssize_t spDeltaAbs = abs(spDelta);
unsigned unwindSpDelta = (unsigned)spDeltaAbs;
assert((ssize_t)unwindSpDelta == spDeltaAbs); // make sure that it fits in a unsigned

 compiler->unwindAllocStack(unwindSpDelta);
 }
}

//------------------------------------------------------------------------
// genPrologSaveRegPair: Save a pair of general-purpose or floating-point/SIMD registers in a function or funclet
// prolog. If possible, we use pre-indexed addressing to adjust SP and store the registers with a single instruction.
// The caller must ensure that we can use the STP instruction, and that spOffset will be in the legal range for that
// instruction.
//
// Arguments:
// reg1 - First register of pair to save.
// reg2 - Second register of pair to save.
// spOffset - The offset from SP to store reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
// useSaveNextPair - True if the last prolog instruction was to save the previous register pair. This
// allows us to emit the "save_next" unwind code.
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.

voidCodeGen::genPrologSaveRegPair(regNumber reg1,
 regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
 regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD

bool needToSaveRegs = true;
if (spDelta != 0)
 {
assert(!useSaveNextPair);
if ((spOffset == 0) && (spDelta >= -512))
 {
// We can use pre-indexed addressing.
// stp REG, REG + 1, [SP, #spDelta]!
// 64-bit STP offset range: -512 to 504, multiple of 8.
GetEmitter()->emitIns_R_R_R_I(INS_stp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spDelta, INS_OPTS_PRE_INDEX);
 compiler->unwindSaveRegPairPreindexed(reg1, reg2, spDelta);

 needToSaveRegs = false;
 }
else// (spOffset != 0) || (spDelta < -512)
 {
// We need to do SP adjustment separately from the store; we can't fold in a pre-indexed addressing and the
// non-zero offset.

// generate sub SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */true);
 }
 }

if (needToSaveRegs)
 {
// stp REG, REG + 1, [SP, #offset]
// 64-bit STP offset range: -512 to 504, multiple of 8.
assert(spOffset <= 504);
GetEmitter()->emitIns_R_R_R_I(INS_stp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);

if (useSaveNextPair)
 {
// This works as long as we've only been saving pairs, in order, and we've saved the previous one just
// before this one.
 compiler->unwindSaveNext();
 }
else
 {
 compiler->unwindSaveRegPair(reg1, reg2, spOffset);
 }
 }
}

//------------------------------------------------------------------------
// genPrologSaveReg: Like genPrologSaveRegPair, but for a single register. Save a single general-purpose or
// floating-point/SIMD register in a function or funclet prolog. Note that if we wish to change SP (i.e., spDelta != 0),
// then spOffset must be 8. This is because otherwise we would create an alignment hole above the saved register, not
// below it, which we currently don't support. This restriction could be loosened if the callers change to handle it
// (and this function changes to support using pre-indexed STR addressing). The caller must ensure that we can use the
// STR instruction, and that spOffset will be in the legal range for that instruction.
//
// Arguments:
// reg1 - Register to save.
// spOffset - The offset from SP to store reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.

voidCodeGen::genPrologSaveReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta <= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned

bool needToSaveRegs = true;
if (spDelta != 0)
 {
if ((spOffset == 0) && (spDelta >= -256))
 {
// We can use pre-index addressing.
// str REG, [SP, #spDelta]!
GetEmitter()->emitIns_R_R_I(INS_str, EA_PTRSIZE, reg1, REG_SPBASE, spDelta, INS_OPTS_PRE_INDEX);
 compiler->unwindSaveRegPreindexed(reg1, spDelta);

 needToSaveRegs = false;
 }
else// (spOffset != 0) || (spDelta < -256)
 {
// generate sub SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */true);
 }
 }

if (needToSaveRegs)
 {
// str REG, [SP, #offset]
// 64-bit STR offset range: 0 to 32760, multiple of 8.
GetEmitter()->emitIns_R_R_I(INS_str, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
 compiler->unwindSaveReg(reg1, spOffset);
 }
}

//------------------------------------------------------------------------
// genEpilogRestoreRegPair: This is the opposite of genPrologSaveRegPair(), run in the epilog instead of the prolog.
// The stack pointer adjustment, if requested, is done after the register restore, using post-index addressing.
// The caller must ensure that we can use the LDP instruction, and that spOffset will be in the legal range for that
// instruction.
//
// Arguments:
// reg1 - First register of pair to restore.
// reg2 - Second register of pair to restore.
// spOffset - The offset from SP to load reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
// useSaveNextPair - True if the last prolog instruction was to save the previous register pair. This
// allows us to emit the "save_next" unwind code.
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.

voidCodeGen::genEpilogRestoreRegPair(regNumber reg1,
 regNumber reg2,
int spOffset,
int spDelta,
bool useSaveNextPair,
 regNumber tmpReg,
bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned
assert(genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2)); // registers must be both general-purpose, or both
// FP/SIMD

if (spDelta != 0)
 {
assert(!useSaveNextPair);
if ((spOffset == 0) && (spDelta <= 504))
 {
// Fold the SP change into this instruction.
// ldp reg1, reg2, [SP], #spDelta
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spDelta, INS_OPTS_POST_INDEX);
 compiler->unwindSaveRegPairPreindexed(reg1, reg2, -spDelta);
 }
else// (spOffset != 0) || (spDelta > 504)
 {
// Can't fold in the SP change; need to use a separate ADD instruction.

// ldp reg1, reg2, [SP, #offset]
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);
 compiler->unwindSaveRegPair(reg1, reg2, spOffset);

// generate add SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */true);
 }
 }
else
 {
GetEmitter()->emitIns_R_R_R_I(INS_ldp, EA_PTRSIZE, reg1, reg2, REG_SPBASE, spOffset);

if (useSaveNextPair)
 {
 compiler->unwindSaveNext();
 }
else
 {
 compiler->unwindSaveRegPair(reg1, reg2, spOffset);
 }
 }
}

//------------------------------------------------------------------------
// genEpilogRestoreReg: The opposite of genPrologSaveReg(), run in the epilog instead of the prolog.
//
// Arguments:
// reg1 - Register to restore.
// spOffset - The offset from SP to restore reg1 (must be positive or zero).
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
// tmpReg - An available temporary register. Needed for the case of large frames.
// pTmpRegIsZero - If we use tmpReg, and pTmpRegIsZero is non-null, we set *pTmpRegIsZero to 'false'.
// Otherwise, we don't touch it.
//
// Return Value:
// None.

voidCodeGen::genEpilogRestoreReg(regNumber reg1, int spOffset, int spDelta, regNumber tmpReg, bool* pTmpRegIsZero)
{
assert(spOffset >= 0);
assert(spDelta >= 0);
assert((spDelta % 16) == 0); // SP changes must be 16-byte aligned

if (spDelta != 0)
 {
if ((spOffset == 0) && (spDelta <= 255))
 {
// We can use post-index addressing.
// ldr REG, [SP], #spDelta
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spDelta, INS_OPTS_POST_INDEX);
 compiler->unwindSaveRegPreindexed(reg1, -spDelta);
 }
else// (spOffset != 0) || (spDelta > 255)
 {
// ldr reg1, [SP, #offset]
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
 compiler->unwindSaveReg(reg1, spOffset);

// generate add SP,SP,imm
genStackPointerAdjustment(spDelta, tmpReg, pTmpRegIsZero, /* reportUnwindData */true);
 }
 }
else
 {
// ldr reg1, [SP, #offset]
GetEmitter()->emitIns_R_R_I(INS_ldr, EA_PTRSIZE, reg1, REG_SPBASE, spOffset);
 compiler->unwindSaveReg(reg1, spOffset);
 }
}

//------------------------------------------------------------------------
// genBuildRegPairsStack: Build a stack of register pairs for prolog/epilog save/restore for the given mask.
// The first register pair will contain the lowest register. Register pairs will combine neighbor
// registers in pairs. If it can't be done (for example if we have a hole or this is the last reg in a mask with
// odd number of regs) then the second element of that RegPair will be REG_NA.
//
// Arguments:
// regsMask - a mask of registers for prolog/epilog generation;
// regStack - a regStack instance to build the stack in, used to save temp copyings.
//
// Return value:
// no return value; the regStack argument is modified.
//
// static
voidCodeGen::genBuildRegPairsStack(regMaskTP regsMask, ArrayStack<RegPair>* regStack)
{
assert(regStack != nullptr);
assert(regStack->Height() == 0);

unsigned regsCount = genCountBits(regsMask);

while (regsMask != RBM_NONE)
 {
 regMaskTP reg1Mask = genFindLowestBit(regsMask);
 regNumber reg1 = genRegNumFromMask(reg1Mask);
 regsMask &= ~reg1Mask;
 regsCount -= 1;

bool isPairSave = false;
if (regsCount > 0)
 {
 regMaskTP reg2Mask = genFindLowestBit(regsMask);
 regNumber reg2 = genRegNumFromMask(reg2Mask);
if (reg2 == REG_NEXT(reg1))
 {
// The JIT doesn't allow saving pair (R28,FP), even though the
// save_regp register pair unwind code specification allows it.
// The JIT always saves (FP,LR) as a pair, and uses the save_fplr
// unwind code. This only comes up in stress mode scenarios
// where callee-saved registers are not allocated completely
// from lowest-to-highest, without gaps.
if (reg1 != REG_R28)
 {
// Both registers must have the same type to be saved as pair.
if (genIsValidFloatReg(reg1) == genIsValidFloatReg(reg2))
 {
 isPairSave = true;

 regsMask &= ~reg2Mask;
 regsCount -= 1;

 regStack->Push(RegPair(reg1, reg2));
 }
 }
 }
 }
if (!isPairSave)
 {
 regStack->Push(RegPair(reg1));
 }
 }
assert(regsCount == 0 && regsMask == RBM_NONE);

genSetUseSaveNextPairs(regStack);
}

//------------------------------------------------------------------------
// genSetUseSaveNextPairs: Set useSaveNextPair for each RegPair on the stack which unwind info can be encoded as
// save_next code.
//
// Arguments:
// regStack - a regStack instance to set useSaveNextPair.
//
// Notes:
// We can use save_next for RegPair(N, N+1) only when we have sequence like (N-2, N-1), (N, N+1).
// In this case in the prolog save_next for (N, N+1) refers to save_pair(N-2, N-1);
// in the epilog the unwinder will search for the first save_pair (N-2, N-1)
// and then go back to the first save_next (N, N+1) to restore it first.
//
// static
voidCodeGen::genSetUseSaveNextPairs(ArrayStack<RegPair>* regStack)
{
for (int i = 1; i < regStack->Height(); ++i)
 {
 RegPair& curr = regStack->BottomRef(i);
 RegPair prev = regStack->Bottom(i - 1);

if (prev.reg2 == REG_NA || curr.reg2 == REG_NA)
 {
continue;
 }

if (REG_NEXT(prev.reg2) != curr.reg1)
 {
continue;
 }

if (genIsValidFloatReg(prev.reg2) != genIsValidFloatReg(curr.reg1))
 {
// It is possible to support changing of the last int pair with the first float pair,
// but it is very rare case and it would require superfluous changes in the unwinder.
continue;
 }
 curr.useSaveNextPair = true;
 }
}

//------------------------------------------------------------------------
// genGetSlotSizeForRegsInMask: Get the stack slot size appropriate for the register type from the mask.
//
// Arguments:
// regsMask - a mask of registers for prolog/epilog generation.
//
// Return value:
// stack slot size in bytes.
//
// Note: Because int and float register type sizes match we can call this function with a mask that includes both.
//
// static
intCodeGen::genGetSlotSizeForRegsInMask(regMaskTP regsMask)
{
assert((regsMask & (RBM_CALLEE_SAVED | RBM_FP | RBM_LR)) == regsMask); // Do not expect anything else.

static_assert_no_msg(REGSIZE_BYTES == FPSAVE_REGSIZE_BYTES);
return REGSIZE_BYTES;
}

//------------------------------------------------------------------------
// genSaveCalleeSavedRegisterGroup: Saves the group of registers described by the mask.
//
// Arguments:
// regsMask - a mask of registers for prolog generation;
// spDelta - if non-zero, the amount to add to SP before the first register save (or together with it);
// spOffset - the offset from SP that is the beginning of the callee-saved register area;
//
voidCodeGen::genSaveCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
constint slotSize = genGetSlotSizeForRegsInMask(regsMask);

 ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, &regStack);

for (int i = 0; i < regStack.Height(); ++i)
 {
 RegPair regPair = regStack.Bottom(i);
if (regPair.reg2 != REG_NA)
 {
// We can use a STP instruction.
genPrologSaveRegPair(regPair.reg1, regPair.reg2, spOffset, spDelta, regPair.useSaveNextPair, REG_IP0,
nullptr);

 spOffset += 2 * slotSize;
 }
else
 {
// No register pair; we use a STR instruction.
genPrologSaveReg(regPair.reg1, spOffset, spDelta, REG_IP0, nullptr);
 spOffset += slotSize;
 }

 spDelta = 0; // We've now changed SP already, if necessary; don't do it again.
 }
}

//------------------------------------------------------------------------
// genSaveCalleeSavedRegistersHelp: Save the callee-saved registers in 'regsToSaveMask' to the stack frame
// in the function or funclet prolog. Registers are saved in register number order from low addresses
// to high addresses. This means that integer registers are saved at lower addresses than floatint-point/SIMD
// registers. However, when genSaveFpLrWithAllCalleeSavedRegisters is true, the integer registers are stored
// at higher addresses than floating-point/SIMD registers, that is, the relative order of these two classes
// is reveresed. This is done to put the saved frame pointer very high in the frame, for simplicity.
//
// TODO: We could always put integer registers at the higher addresses, if desired, to remove this special
// case. It would cause many asm diffs when first implemented.
//
// If establishing frame pointer chaining, it must be done after saving the callee-saved registers.
//
// We can only use the instructions that are allowed by the unwind codes. The caller ensures that
// there is enough space on the frame to store these registers, and that the store instructions
// we need to use (STR or STP) are encodable with the stack-pointer immediate offsets we need to use.
//
// The caller can tell us to fold in a stack pointer adjustment, which we will do with the first instruction.
// Note that the stack pointer adjustment must be by a multiple of 16 to preserve the invariant that the
// stack pointer is always 16 byte aligned. If we are saving an odd number of callee-saved
// registers, though, we will have an empty aligment slot somewhere. It turns out we will put
// it below (at a lower address) the callee-saved registers, as that is currently how we
// do frame layout. This means that the first stack offset will be 8 and the stack pointer
// adjustment must be done by a SUB, and not folded in to a pre-indexed store.
//
// Arguments:
// regsToSaveMask - The mask of callee-saved registers to save. If empty, this function does nothing.
// lowestCalleeSavedOffset - The offset from SP that is the beginning of the callee-saved register area. Note that
// if non-zero spDelta, then this is the offset of the first save *after* that
// SP adjustment.
// spDelta - If non-zero, the amount to add to SP before the register saves (must be negative or
// zero).
//
// Notes:
// The save set can contain LR in which case LR is saved along with the other callee-saved registers.
// But currently Jit doesn't use frames without frame pointer on arm64.
//
voidCodeGen::genSaveCalleeSavedRegistersHelp(regMaskTP regsToSaveMask, int lowestCalleeSavedOffset, int spDelta)
{
assert(spDelta <= 0);
assert(-spDelta <= STACK_PROBE_BOUNDARY_THRESHOLD_BYTES);

unsigned regsToSaveCount = genCountBits(regsToSaveMask);
if (regsToSaveCount == 0)
 {
if (spDelta != 0)
 {
// Currently this is the case for varargs only
// whose size is MAX_REG_ARG * REGSIZE_BYTES = 64 bytes.
genStackPointerAdjustment(spDelta, REG_NA, nullptr, /* reportUnwindData */true);
 }
return;
 }

assert((spDelta % 16) == 0);

// We also can save FP and LR, even though they are not in RBM_CALLEE_SAVED.
assert(regsToSaveCount <= genCountBits(RBM_CALLEE_SAVED | RBM_FP | RBM_LR));

// Save integer registers at higher addresses than floating-point registers.

 regMaskTP maskSaveRegsFloat = regsToSaveMask & RBM_ALLFLOAT;
 regMaskTP maskSaveRegsInt = regsToSaveMask & ~maskSaveRegsFloat;

if (maskSaveRegsFloat != RBM_NONE)
 {
genSaveCalleeSavedRegisterGroup(maskSaveRegsFloat, spDelta, lowestCalleeSavedOffset);
 spDelta = 0;
 lowestCalleeSavedOffset += genCountBits(maskSaveRegsFloat) * FPSAVE_REGSIZE_BYTES;
 }

if (maskSaveRegsInt != RBM_NONE)
 {
genSaveCalleeSavedRegisterGroup(maskSaveRegsInt, spDelta, lowestCalleeSavedOffset);
// No need to update spDelta, lowestCalleeSavedOffset since they're not used after this.
 }
}

//------------------------------------------------------------------------
// genRestoreCalleeSavedRegisterGroup: Restores the group of registers described by the mask.
//
// Arguments:
// regsMask - a mask of registers for epilog generation;
// spDelta - if non-zero, the amount to add to SP after the last register restore (or together with it);
// spOffset - the offset from SP that is the beginning of the callee-saved register area;
//
voidCodeGen::genRestoreCalleeSavedRegisterGroup(regMaskTP regsMask, int spDelta, int spOffset)
{
constint slotSize = genGetSlotSizeForRegsInMask(regsMask);

 ArrayStack<RegPair> regStack(compiler->getAllocator(CMK_Codegen));
genBuildRegPairsStack(regsMask, &regStack);

int stackDelta = 0;
for (int i = 0; i < regStack.Height(); ++i)
 {
bool lastRestoreInTheGroup = (i == regStack.Height() - 1);
bool updateStackDelta = lastRestoreInTheGroup && (spDelta != 0);
if (updateStackDelta)
 {
// Update stack delta only if it is the last restore (the first save).
assert(stackDelta == 0);
 stackDelta = spDelta;
 }

 RegPair regPair = regStack.Top(i);
if (regPair.reg2 != REG_NA)
 {
 spOffset -= 2 * slotSize;

genEpilogRestoreRegPair(regPair.reg1, regPair.reg2, spOffset, stackDelta, regPair.useSaveNextPair, REG_IP1,
nullptr);
 }
else
 {
 spOffset -= slotSize;
genEpilogRestoreReg(regPair.reg1, spOffset, stackDelta, REG_IP1, nullptr);
 }
 }
}

//------------------------------------------------------------------------
// genRestoreCalleeSavedRegistersHelp: Restore the callee-saved registers in 'regsToRestoreMask' from the stack frame
// in the function or funclet epilog. This exactly reverses the actions of genSaveCalleeSavedRegistersHelp().
//
// Arguments:
// regsToRestoreMask - The mask of callee-saved registers to restore. If empty, this function does nothing.
// lowestCalleeSavedOffset - The offset from SP that is the beginning of the callee-saved register area.
// spDelta - If non-zero, the amount to add to SP after the register restores (must be positive or
// zero).
//
// Here's an example restore sequence:
// ldp x27, x28, [sp,#96]
// ldp x25, x26, [sp,#80]
// ldp x23, x24, [sp,#64]
// ldp x21, x22, [sp,#48]
// ldp x19, x20, [sp,#32]
//
// For the case of non-zero spDelta, we assume the base of the callee-save registers to restore is at SP, and
// the last restore adjusts SP by the specified amount. For example:
// ldp x27, x28, [sp,#64]
// ldp x25, x26, [sp,#48]
// ldp x23, x24, [sp,#32]
// ldp x21, x22, [sp,#16]
// ldp x19, x20, [sp], #80
//
// Note you call the unwind functions specifying the prolog operation that is being un-done. So, for example, when
// generating a post-indexed load, you call the unwind function for specifying the corresponding preindexed store.
//
// Return Value:
// None.

voidCodeGen::genRestoreCalleeSavedRegistersHelp(regMaskTP regsToRestoreMask, int lowestCalleeSavedOffset, int spDelta)
{
assert(spDelta >= 0);
unsigned regsToRestoreCount = genCountBits(regsToRestoreMask);
if (regsToRestoreCount == 0)
 {
if (spDelta != 0)
 {
// Currently this is the case for varargs only
// whose size is MAX_REG_ARG * REGSIZE_BYTES = 64 bytes.
genStackPointerAdjustment(spDelta, REG_NA, nullptr, /* reportUnwindData */true);
 }
return;
 }

assert((spDelta % 16) == 0);

// We also can restore FP and LR, even though they are not in RBM_CALLEE_SAVED.
assert(regsToRestoreCount <= genCountBits(RBM_CALLEE_SAVED | RBM_FP | RBM_LR));

// Point past the end, to start. We predecrement to find the offset to load from.
static_assert_no_msg(REGSIZE_BYTES == FPSAVE_REGSIZE_BYTES);
int spOffset = lowestCalleeSavedOffset + regsToRestoreCount * REGSIZE_BYTES;

// Save integer registers at higher addresses than floating-point registers.

 regMaskTP maskRestoreRegsFloat = regsToRestoreMask & RBM_ALLFLOAT;
 regMaskTP maskRestoreRegsInt = regsToRestoreMask & ~maskRestoreRegsFloat;

// Restore in the opposite order of saving.

if (maskRestoreRegsInt != RBM_NONE)
 {
int spIntDelta = (maskRestoreRegsFloat != RBM_NONE) ? 0 : spDelta; // should we delay the SP adjustment?
genRestoreCalleeSavedRegisterGroup(maskRestoreRegsInt, spIntDelta, spOffset);
 spOffset -= genCountBits(maskRestoreRegsInt) * REGSIZE_BYTES;
 }

if (maskRestoreRegsFloat != RBM_NONE)
 {
// If there is any spDelta, it must be used here.
genRestoreCalleeSavedRegisterGroup(maskRestoreRegsFloat, spDelta, spOffset);
// No need to update spOffset since it's not used after this.
 }
}

// clang-format off
/*****************************************************************************
 *
 * Generates code for an EH funclet prolog.
 *
 * Funclets have the following incoming arguments:
 *
 * catch: x0 = the exception object that was caught (see GT_CATCH_ARG)
 * filter: x0 = the exception object to filter (see GT_CATCH_ARG), x1 = CallerSP of the containing function
 * finally/fault: none
 *
 * Funclets set the following registers on exit:
 *
 * catch: x0 = the address at which execution should resume (see BBJ_EHCATCHRET)
 * filter: x0 = non-zero if the handler should handle the exception, zero otherwise (see GT_RETFILT)
 * finally/fault: none
 *
 * The ARM64 funclet prolog sequence is one of the following (Note: #framesz is total funclet frame size,
 * including everything; #outsz is outgoing argument space. #framesz must be a multiple of 16):
 *
 * Frame type 1:
 * For #outsz == 0 and #framesz <= 512:
 * stp fp,lr,[sp,-#framesz]! ; establish the frame (predecrement by #framesz), save FP/LR
 * stp x19,x20,[sp,#xxx] ; save callee-saved registers, as necessary
 *
 * The funclet frame is thus:
 *
 * | |
 * |-----------------------|
 * | incoming arguments |
 * +=======================+ <---- Caller's SP
 * | Varargs regs space | // Only for varargs main functions; 64 bytes
 * |-----------------------|
 * |Callee saved registers | // multiple of 8 bytes
 * |-----------------------|
 * | PSP slot | // 8 bytes (omitted in CoreRT ABI)
 * |-----------------------|
 * ~ alignment padding ~ // To make the whole frame 16 byte aligned.
 * |-----------------------|
 * | Saved FP, LR | // 16 bytes
 * |-----------------------| <---- Ambient SP
 * | | |
 * ~ | Stack grows ~
 * | | downward |
 * V
 *
 * Frame type 2:
 * For #outsz != 0 and #framesz <= 512:
 * sub sp,sp,#framesz ; establish the frame
 * stp fp,lr,[sp,#outsz] ; save FP/LR.
 * stp x19,x20,[sp,#xxx] ; save callee-saved registers, as necessary
 *
 * The funclet frame is thus:
 *
 * | |
 * |-----------------------|
 * | incoming arguments |
 * +=======================+ <---- Caller's SP
 * | Varargs regs space | // Only for varargs main functions; 64 bytes
 * |-----------------------|
 * |Callee saved registers | // multiple of 8 bytes
 * |-----------------------|
 * | PSP slot | // 8 bytes (omitted in CoreRT ABI)
 * |-----------------------|
 * ~ alignment padding ~ // To make the whole frame 16 byte aligned.
 * |-----------------------|
 * | Saved FP, LR | // 16 bytes
 * |-----------------------|
 * | Outgoing arg space | // multiple of 8 bytes
 * |-----------------------| <---- Ambient SP
 * | | |
 * ~ | Stack grows ~
 * | | downward |
 * V
 *
 * Frame type 3:
 * For #framesz > 512:
 * stp fp,lr,[sp,- (#framesz - #outsz)]! ; establish the frame, save FP/LR
 * ; note that it is guaranteed here that (#framesz - #outsz) <= 240
 * stp x19,x20,[sp,#xxx] ; save callee-saved registers, as necessary
 * sub sp,sp,#outsz ; create space for outgoing argument space
 *
 * The funclet frame is thus:
 *
 * | |
 * |-----------------------|
 * | incoming arguments |
 * +=======================+ <---- Caller's SP
 * | Varargs regs space | // Only for varargs main functions; 64 bytes
 * |-----------------------|
 * |Callee saved registers | // multiple of 8 bytes
 * |-----------------------|
 * | PSP slot | // 8 bytes (omitted in CoreRT ABI)
 * |-----------------------|
 * ~ alignment padding ~ // To make the first SP subtraction 16 byte aligned
 * |-----------------------|
 * | Saved FP, LR | // 16 bytes
 * |-----------------------|
 * ~ alignment padding ~ // To make the whole frame 16 byte aligned (specifically, to 16-byte align the outgoing argument space).
 * |-----------------------|
 * | Outgoing arg space | // multiple of 8 bytes
 * |-----------------------| <---- Ambient SP
 * | | |
 * ~ | Stack grows ~
 * | | downward |
 * V
 *
 * Both #1 and #2 only change SP once. That means that there will be a maximum of one alignment slot needed. For the general case, #3,
 * it is possible that we will need to add alignment to both changes to SP, leading to 16 bytes of alignment. Remember that the stack
 * pointer needs to be 16 byte aligned at all times. The size of the PSP slot plus callee-saved registers space is a maximum of 240 bytes:
 *
 * FP,LR registers
 * 10 int callee-saved register x19-x28
 * 8 float callee-saved registers v8-v15
 * 8 saved integer argument registers x0-x7, if varargs function
 * 1 PSP slot
 * 1 alignment slot
 * == 30 slots * 8 bytes = 240 bytes.
 *
 * The outgoing argument size, however, can be very large, if we call a function that takes a large number of
 * arguments (note that we currently use the same outgoing argument space size in the funclet as for the main
 * function, even if the funclet doesn't have any calls, or has a much smaller, or larger, maximum number of
 * outgoing arguments for any call). In that case, we need to 16-byte align the initial change to SP, before
 * saving off the callee-saved registers and establishing the PSPsym, so we can use the limited immediate offset
 * encodings we have available, before doing another 16-byte aligned SP adjustment to create the outgoing argument
 * space. Both changes to SP might need to add alignment padding.
 *
 * In addition to the above "standard" frames, we also need to support a frame where the saved FP/LR are at the
 * highest addresses. This is to match the frame layout (specifically, callee-saved registers including FP/LR
 * and the PSPSym) that is used in the main function when a GS cookie is required due to the use of localloc.
 * (Note that localloc cannot be used in a funclet.) In these variants, not only has the position of FP/LR
 * changed, but where the alignment padding is placed has also changed.
 *
 * Frame type 4 (variant of frame types 1 and 2):
 * For #framesz <= 512:
 * sub sp,sp,#framesz ; establish the frame
 * stp x19,x20,[sp,#xxx] ; save callee-saved registers, as necessary
 * stp fp,lr,[sp,#yyy] ; save FP/LR.
 * ; write PSPSym
 *
 * The "#framesz <= 512" condition ensures that after we've established the frame, we can use "stp" with its
 * maximum allowed offset (504) to save the callee-saved register at the highest address.
 *
 * We use "sub" instead of folding it into the next instruction as a predecrement, as we need to write PSPSym
 * at the bottom of the stack, and there might also be an alignment padding slot.
 *
 * The funclet frame is thus:
 *
 * | |
 * |-----------------------|
 * | incoming arguments |
 * +=======================+ <---- Caller's SP
 * | Varargs regs space | // Only for varargs main functions; 64 bytes
 * |-----------------------|
 * | Saved LR | // 8 bytes
 * |-----------------------|
 * | Saved FP | // 8 bytes
 * |-----------------------|
 * |Callee saved registers | // multiple of 8 bytes
 * |-----------------------|
 * | PSP slot | // 8 bytes (omitted in CoreRT ABI)
 * |-----------------------|
 * ~ alignment padding ~ // To make the whole frame 16 byte aligned.
 * |-----------------------|
 * | Outgoing arg space | // multiple of 8 bytes (optional; if #outsz > 0)
 * |-----------------------| <---- Ambient SP
 * | | |
 * ~ | Stack grows ~
 * | | downward |
 * V
 *
 * Frame type 5 (variant of frame type 3):
 * For #framesz > 512:
 * sub sp,sp,(#framesz - #outsz) ; establish part of the frame. Note that it is guaranteed here that (#framesz - #outsz) <= 240
 * stp x19,x20,[sp,#xxx] ; save callee-saved registers, as necessary
 * stp fp,lr,[sp,#yyy] ; save FP/LR.
 * sub sp,sp,#outsz ; create space for outgoing argument space
 * ; write PSPSym
 *
 * For large frames with "#framesz > 512", we must do one SP adjustment first, after which we can save callee-saved
 * registers with up to the maximum "stp" offset of 504. Then, we can establish the rest of the frame (namely, the
 * space for the outgoing argument space).
 *
 * The funclet frame is thus:
 *
 * | |
 * |-----------------------|
 * | incoming arguments |
 * +=======================+ <---- Caller's SP
 * | Varargs regs space | // Only for varargs main functions; 64 bytes
 * |-----------------------|
 * | Saved LR | // 8 bytes
 * |-----------------------|
 * | Saved FP | // 8 bytes
 * |-----------------------|
 * |Callee saved registers | // multiple of 8 bytes
 * |-----------------------|
 * | PSP slot | // 8 bytes (omitted in CoreRT ABI)
 * |-----------------------|
 * ~ alignment padding ~ // To make the first SP subtraction 16 byte aligned
 * |-----------------------|
 * ~ alignment padding ~ // To make the whole frame 16 byte aligned (specifically, to 16-byte align the outgoing argument space).
 * |-----------------------|
 * | Outgoing arg space | // multiple of 8 bytes
 * |-----------------------| <---- Ambient SP
 * | | |