opcodes.py

fromuctypesimportUINT32, BFUINT32, BF_POS, BF_LEN
fromesp32_ulp.opcodesimportmake_ins, make_ins_struct_def
fromesp32_ulp.opcodesimportget_reg, get_imm, get_cond, arg_qualify, eval_arg, ARG, REG, IMM, SYM, COND
fromesp32_ulp.assembleimportSymbolTable, ABS, REL, TEXT
importesp32_ulp.opcodesasopcodes

OPCODE_DELAY=4
LAYOUT_DELAY="""
 cycles : 16 # Number of cycles to sleep
 unused : 12 # Unused
 opcode : 4 # Opcode (OPCODE_DELAY)
"""


deftest_make_ins_struct_def():
sd=make_ins_struct_def(LAYOUT_DELAY)
assertset(sd) == {'cycles', 'unused', 'opcode', 'all'}
assertsd['cycles'] ==BFUINT32|0<<BF_POS|16<<BF_LEN
assertsd['unused'] ==BFUINT32|16<<BF_POS|12<<BF_LEN
assertsd['opcode'] ==BFUINT32|28<<BF_POS|4<<BF_LEN
assertsd['all'] ==UINT32


deftest_make_ins():
_delay=make_ins(LAYOUT_DELAY)
_delay.cycles=0x23
_delay.unused=0
_delay.opcode=OPCODE_DELAY
assert_delay.cycles==0x23
assert_delay.unused==0
assert_delay.opcode==OPCODE_DELAY
assert_delay.all==0x40000023


deftest_arg_qualify():
assertarg_qualify('r0') ==ARG(REG, 0, 'r0')
assertarg_qualify('R3') ==ARG(REG, 3, 'R3')
assertarg_qualify('0') ==ARG(IMM, 0, '0')
assertarg_qualify('-1') ==ARG(IMM, -1, '-1')
assertarg_qualify('1') ==ARG(IMM, 1, '1')
assertarg_qualify('0x20') ==ARG(IMM, 32, '0x20')
assertarg_qualify('0o100') ==ARG(IMM, 64, '0o100')
assertarg_qualify('0b1000') ==ARG(IMM, 8, '0b1000')
assertarg_qualify('eq') ==ARG(COND, 'eq', 'eq')
assertarg_qualify('Eq') ==ARG(COND, 'eq', 'Eq')
assertarg_qualify('EQ') ==ARG(COND, 'eq', 'EQ')

# for the next tests, ensure the opcodes module has a SymbolTable
opcodes.symbols=SymbolTable({}, {}, {})
opcodes.symbols.set_sym('const', ABS, None, 42) # constant as defined by .set
opcodes.symbols.set_sym('entry', REL, TEXT, 4) # label pointing to code

assertarg_qualify('1+1') ==ARG(IMM, 2, '1+1')
assertarg_qualify('const >> 1') ==ARG(IMM, 21, 'const >> 1')
assertarg_qualify('entry') ==ARG(SYM, (REL, TEXT, 4), 'entry') # symbols should not (yet) be evaluated
assertarg_qualify('entry + const') ==ARG(IMM, 46, 'entry + const')

# clean up
opcodes.symbols=None


deftest_get_reg():
assertget_reg('r0') ==0
assertget_reg('R3') ==3


deftest_get_imm():
assertget_imm('42') ==42


deftest_get_cond():
assertget_cond('Eq') =='eq'


deftest_eval_arg():
opcodes.symbols=SymbolTable({}, {}, {})
opcodes.symbols.set_sym('const', ABS, None, 42) # constant
opcodes.symbols.set_sym('raise', ABS, None, 99) # constant using a python keyword as name (is allowed)

asserteval_arg('1+1') ==2
asserteval_arg('1+const') ==43
asserteval_arg('raise*2/3') ==66
asserteval_arg('raise-const') ==57
asserteval_arg('(raise-const)*2') ==114
asserteval_arg('const % 5') ==2
asserteval_arg('const + 0x19af') ==0x19af+42
asserteval_arg('const & ~2') ==40
asserteval_arg('const << 3') ==336
asserteval_arg('const >> 1') ==21
asserteval_arg('(const|4)&0xf') ==0xe

assert_raises(ValueError, eval_arg, 'evil()')
assert_raises(ValueError, eval_arg, 'def cafe()')
assert_raises(ValueError, eval_arg, '1 ^ 2')
assert_raises(ValueError, eval_arg, '!100')

# clean up
opcodes.symbols=None


defassert_raises(exception, func, *args):
try:
func(*args)
exceptexception:
raised=True
else:
raised=False
assertraised


deftest_reg_direct_ulp_addressing():
"""
 Test direct ULP addressing of peripheral registers
 input must be <= 0x3ff (10 bits)
 periph_sel == high 2 bits from input
 addr == low 8 bits from input
 """

ins=make_ins("""
 addr : 8 # Address within either RTC_CNTL, RTC_IO, or SARADC
 periph_sel : 2 # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
 unused : 8 # Unused
 low : 5 # Low bit
 high : 5 # High bit
 opcode : 4 # Opcode (OPCODE_RD_REG)
 """)

ins.all=opcodes.i_reg_rd("0x0", "0", "0")
assertins.periph_sel==0
assertins.addr==0x0

ins.all=opcodes.i_reg_rd("0x012", "0", "0")
assertins.periph_sel==0
assertins.addr==0x12

ins.all=opcodes.i_reg_rd("0x123", "0", "0")
assertins.periph_sel==1
assertins.addr==0x23

ins.all=opcodes.i_reg_rd("0x2ee", "0", "0")
assertins.periph_sel==2
assertins.addr==0xee

ins.all=opcodes.i_reg_rd("0x3ff", "0", "0")
assertins.periph_sel==3
assertins.addr==0xff

# anything bigger than 0x3ff must be a valid full address
assert_raises(ValueError, opcodes.i_reg_rd, "0x400", "0", "0")


deftest_reg_address_translations():
"""
 Test addressing of peripheral registers using full DPORT bus addresses
 """

ins=make_ins("""
 addr : 8 # Address within either RTC_CNTL, RTC_IO, or SARADC
 periph_sel : 2 # Select peripheral: RTC_CNTL (0), RTC_IO(1), SARADC(2)
 unused : 8 # Unused
 low : 5 # Low bit
 high : 5 # High bit
 opcode : 4 # Opcode (OPCODE_RD_REG)
 """)

# direct ULP address is derived from full address as follows:
# full:0x3ff484a8 == ulp:(0x3ff484a8-DR_REG_RTCCNTL_BASE) / 4
# full:0x3ff484a8 == ulp:(0x3ff484a8-0x3ff48000) / 4
# full:0x3ff484a8 == ulp:0x4a8 / 4
# full:0x3ff484a8 == ulp:0x12a
# see: https://github.com/espressif/binutils-esp32ulp/blob/249ec34/gas/config/tc-esp32ulp_esp32.c#L149
ins.all=opcodes.i_reg_rd("0x3ff484a8", "0", "0")
assertins.periph_sel==1# high 2 bits of 0x12a
assertins.addr==0x2a# low 8 bits of 0x12a


test_make_ins_struct_def()
test_make_ins()
test_arg_qualify()
test_get_reg()
test_get_imm()
test_get_cond()
test_eval_arg()
test_reg_direct_ulp_addressing()
test_reg_address_translations()